RTOS 1.0
stm32f439xx.h
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33#ifndef __STM32F439xx_H
34#define __STM32F439xx_H
35
36#ifdef __cplusplus
37extern "C" {
38#endif /* __cplusplus */
39
43
47#define __CM4_REV 0x0001U
48#define __MPU_PRESENT 1U
49#define __NVIC_PRIO_BITS 4U
50#define __Vendor_SysTickConfig 0U
51#define __FPU_PRESENT 1U
52
56
60
65typedef enum
66{
67 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
68 NonMaskableInt_IRQn = -14,
69 MemoryManagement_IRQn = -12,
70 BusFault_IRQn = -11,
71 UsageFault_IRQn = -10,
72 SVCall_IRQn = -5,
73 DebugMonitor_IRQn = -4,
74 PendSV_IRQn = -2,
75 SysTick_IRQn = -1,
76 /****** STM32 specific Interrupt Numbers **********************************************************************/
77 WWDG_IRQn = 0,
78 PVD_IRQn = 1,
79 TAMP_STAMP_IRQn = 2,
80 RTC_WKUP_IRQn = 3,
81 FLASH_IRQn = 4,
82 RCC_IRQn = 5,
83 EXTI0_IRQn = 6,
84 EXTI1_IRQn = 7,
85 EXTI2_IRQn = 8,
86 EXTI3_IRQn = 9,
87 EXTI4_IRQn = 10,
88 DMA1_Stream0_IRQn = 11,
89 DMA1_Stream1_IRQn = 12,
90 DMA1_Stream2_IRQn = 13,
91 DMA1_Stream3_IRQn = 14,
92 DMA1_Stream4_IRQn = 15,
93 DMA1_Stream5_IRQn = 16,
94 DMA1_Stream6_IRQn = 17,
95 ADC_IRQn = 18,
96 CAN1_TX_IRQn = 19,
97 CAN1_RX0_IRQn = 20,
98 CAN1_RX1_IRQn = 21,
99 CAN1_SCE_IRQn = 22,
100 EXTI9_5_IRQn = 23,
101 TIM1_BRK_TIM9_IRQn = 24,
102 TIM1_UP_TIM10_IRQn = 25,
103 TIM1_TRG_COM_TIM11_IRQn = 26,
104 TIM1_CC_IRQn = 27,
105 TIM2_IRQn = 28,
106 TIM3_IRQn = 29,
107 TIM4_IRQn = 30,
108 I2C1_EV_IRQn = 31,
109 I2C1_ER_IRQn = 32,
110 I2C2_EV_IRQn = 33,
111 I2C2_ER_IRQn = 34,
112 SPI1_IRQn = 35,
113 SPI2_IRQn = 36,
114 USART1_IRQn = 37,
115 USART2_IRQn = 38,
116 USART3_IRQn = 39,
117 EXTI15_10_IRQn = 40,
118 RTC_Alarm_IRQn = 41,
119 OTG_FS_WKUP_IRQn = 42,
120 TIM8_BRK_TIM12_IRQn = 43,
121 TIM8_UP_TIM13_IRQn = 44,
122 TIM8_TRG_COM_TIM14_IRQn = 45,
123 TIM8_CC_IRQn = 46,
124 DMA1_Stream7_IRQn = 47,
125 FMC_IRQn = 48,
126 SDIO_IRQn = 49,
127 TIM5_IRQn = 50,
128 SPI3_IRQn = 51,
129 UART4_IRQn = 52,
130 UART5_IRQn = 53,
131 TIM6_DAC_IRQn = 54,
132 TIM7_IRQn = 55,
133 DMA2_Stream0_IRQn = 56,
134 DMA2_Stream1_IRQn = 57,
135 DMA2_Stream2_IRQn = 58,
136 DMA2_Stream3_IRQn = 59,
137 DMA2_Stream4_IRQn = 60,
138 ETH_IRQn = 61,
139 ETH_WKUP_IRQn = 62,
140 CAN2_TX_IRQn = 63,
141 CAN2_RX0_IRQn = 64,
142 CAN2_RX1_IRQn = 65,
143 CAN2_SCE_IRQn = 66,
144 OTG_FS_IRQn = 67,
145 DMA2_Stream5_IRQn = 68,
146 DMA2_Stream6_IRQn = 69,
147 DMA2_Stream7_IRQn = 70,
148 USART6_IRQn = 71,
149 I2C3_EV_IRQn = 72,
150 I2C3_ER_IRQn = 73,
151 OTG_HS_EP1_OUT_IRQn = 74,
152 OTG_HS_EP1_IN_IRQn = 75,
153 OTG_HS_WKUP_IRQn = 76,
154 OTG_HS_IRQn = 77,
155 DCMI_IRQn = 78,
156 CRYP_IRQn = 79,
157 HASH_RNG_IRQn = 80,
158 FPU_IRQn = 81,
159 UART7_IRQn = 82,
160 UART8_IRQn = 83,
161 SPI4_IRQn = 84,
162 SPI5_IRQn = 85,
163 SPI6_IRQn = 86,
164 SAI1_IRQn = 87,
165 LTDC_IRQn = 88,
166 LTDC_ER_IRQn = 89,
167 DMA2D_IRQn = 90
168} IRQn_Type;
169
173
174#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
175#include "system_stm32f4xx.h"
176#include <stdint.h>
177
181
185
186typedef struct
187{
188 __IO uint32_t SR;
189 __IO uint32_t CR1;
190 __IO uint32_t CR2;
191 __IO uint32_t SMPR1;
192 __IO uint32_t SMPR2;
193 __IO uint32_t JOFR1;
194 __IO uint32_t JOFR2;
195 __IO uint32_t JOFR3;
196 __IO uint32_t JOFR4;
197 __IO uint32_t HTR;
198 __IO uint32_t LTR;
199 __IO uint32_t SQR1;
200 __IO uint32_t SQR2;
201 __IO uint32_t SQR3;
202 __IO uint32_t JSQR;
203 __IO uint32_t JDR1;
204 __IO uint32_t JDR2;
205 __IO uint32_t JDR3;
206 __IO uint32_t JDR4;
207 __IO uint32_t DR;
208} ADC_TypeDef;
209
210typedef struct
211{
212 __IO uint32_t CSR;
213 __IO uint32_t CCR;
214 __IO uint32_t CDR;
216} ADC_Common_TypeDef;
217
218
222
223typedef struct
224{
225 __IO uint32_t TIR;
226 __IO uint32_t TDTR;
227 __IO uint32_t TDLR;
228 __IO uint32_t TDHR;
229} CAN_TxMailBox_TypeDef;
230
234
235typedef struct
236{
237 __IO uint32_t RIR;
238 __IO uint32_t RDTR;
239 __IO uint32_t RDLR;
240 __IO uint32_t RDHR;
241} CAN_FIFOMailBox_TypeDef;
242
246
247typedef struct
248{
249 __IO uint32_t FR1;
250 __IO uint32_t FR2;
251} CAN_FilterRegister_TypeDef;
252
256
257typedef struct
258{
259 __IO uint32_t MCR;
260 __IO uint32_t MSR;
261 __IO uint32_t TSR;
262 __IO uint32_t RF0R;
263 __IO uint32_t RF1R;
264 __IO uint32_t IER;
265 __IO uint32_t ESR;
266 __IO uint32_t BTR;
267 uint32_t RESERVED0[88];
268 CAN_TxMailBox_TypeDef sTxMailBox[3];
269 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
270 uint32_t RESERVED1[12];
271 __IO uint32_t FMR;
272 __IO uint32_t FM1R;
273 uint32_t RESERVED2;
274 __IO uint32_t FS1R;
275 uint32_t RESERVED3;
276 __IO uint32_t FFA1R;
277 uint32_t RESERVED4;
278 __IO uint32_t FA1R;
279 uint32_t RESERVED5[8];
280 CAN_FilterRegister_TypeDef sFilterRegister[28];
281} CAN_TypeDef;
282
286
287typedef struct
288{
289 __IO uint32_t DR;
290 __IO uint8_t IDR;
291 uint8_t RESERVED0;
292 uint16_t RESERVED1;
293 __IO uint32_t CR;
294} CRC_TypeDef;
295
299
300typedef struct
301{
302 __IO uint32_t CR;
303 __IO uint32_t SWTRIGR;
304 __IO uint32_t DHR12R1;
305 __IO uint32_t DHR12L1;
306 __IO uint32_t DHR8R1;
307 __IO uint32_t DHR12R2;
308 __IO uint32_t DHR12L2;
309 __IO uint32_t DHR8R2;
310 __IO uint32_t DHR12RD;
311 __IO uint32_t DHR12LD;
312 __IO uint32_t DHR8RD;
313 __IO uint32_t DOR1;
314 __IO uint32_t DOR2;
315 __IO uint32_t SR;
316} DAC_TypeDef;
317
321
322typedef struct
323{
324 __IO uint32_t IDCODE;
325 __IO uint32_t CR;
326 __IO uint32_t APB1FZ;
327 __IO uint32_t APB2FZ;
328} DBGMCU_TypeDef;
329
333
334typedef struct
335{
336 __IO uint32_t CR;
337 __IO uint32_t SR;
338 __IO uint32_t RISR;
339 __IO uint32_t IER;
340 __IO uint32_t MISR;
341 __IO uint32_t ICR;
342 __IO uint32_t ESCR;
343 __IO uint32_t ESUR;
344 __IO uint32_t CWSTRTR;
345 __IO uint32_t CWSIZER;
346 __IO uint32_t DR;
347} DCMI_TypeDef;
348
352
353typedef struct
354{
355 __IO uint32_t CR;
356 __IO uint32_t NDTR;
357 __IO uint32_t PAR;
358 __IO uint32_t M0AR;
359 __IO uint32_t M1AR;
360 __IO uint32_t FCR;
361} DMA_Stream_TypeDef;
362
363typedef struct
364{
365 __IO uint32_t LISR;
366 __IO uint32_t HISR;
367 __IO uint32_t LIFCR;
368 __IO uint32_t HIFCR;
369} DMA_TypeDef;
370
374
375typedef struct
376{
377 __IO uint32_t CR;
378 __IO uint32_t ISR;
379 __IO uint32_t IFCR;
380 __IO uint32_t FGMAR;
381 __IO uint32_t FGOR;
382 __IO uint32_t BGMAR;
383 __IO uint32_t BGOR;
384 __IO uint32_t FGPFCCR;
385 __IO uint32_t FGCOLR;
386 __IO uint32_t BGPFCCR;
387 __IO uint32_t BGCOLR;
388 __IO uint32_t FGCMAR;
389 __IO uint32_t BGCMAR;
390 __IO uint32_t OPFCCR;
391 __IO uint32_t OCOLR;
392 __IO uint32_t OMAR;
393 __IO uint32_t OOR;
394 __IO uint32_t NLR;
395 __IO uint32_t LWR;
396 __IO uint32_t AMTCR;
397 uint32_t RESERVED[236];
398 __IO uint32_t FGCLUT[256];
399 __IO uint32_t BGCLUT[256];
400} DMA2D_TypeDef;
401
405
406typedef struct
407{
408 __IO uint32_t MACCR;
409 __IO uint32_t MACFFR;
410 __IO uint32_t MACHTHR;
411 __IO uint32_t MACHTLR;
412 __IO uint32_t MACMIIAR;
413 __IO uint32_t MACMIIDR;
414 __IO uint32_t MACFCR;
415 __IO uint32_t MACVLANTR; /* 8 */
416 uint32_t RESERVED0[2];
417 __IO uint32_t MACRWUFFR; /* 11 */
418 __IO uint32_t MACPMTCSR;
419 uint32_t RESERVED1;
420 __IO uint32_t MACDBGR;
421 __IO uint32_t MACSR; /* 15 */
422 __IO uint32_t MACIMR;
423 __IO uint32_t MACA0HR;
424 __IO uint32_t MACA0LR;
425 __IO uint32_t MACA1HR;
426 __IO uint32_t MACA1LR;
427 __IO uint32_t MACA2HR;
428 __IO uint32_t MACA2LR;
429 __IO uint32_t MACA3HR;
430 __IO uint32_t MACA3LR; /* 24 */
431 uint32_t RESERVED2[40];
432 __IO uint32_t MMCCR; /* 65 */
433 __IO uint32_t MMCRIR;
434 __IO uint32_t MMCTIR;
435 __IO uint32_t MMCRIMR;
436 __IO uint32_t MMCTIMR; /* 69 */
437 uint32_t RESERVED3[14];
438 __IO uint32_t MMCTGFSCCR; /* 84 */
439 __IO uint32_t MMCTGFMSCCR;
440 uint32_t RESERVED4[5];
441 __IO uint32_t MMCTGFCR;
442 uint32_t RESERVED5[10];
443 __IO uint32_t MMCRFCECR;
444 __IO uint32_t MMCRFAECR;
445 uint32_t RESERVED6[10];
446 __IO uint32_t MMCRGUFCR;
447 uint32_t RESERVED7[334];
448 __IO uint32_t PTPTSCR;
449 __IO uint32_t PTPSSIR;
450 __IO uint32_t PTPTSHR;
451 __IO uint32_t PTPTSLR;
452 __IO uint32_t PTPTSHUR;
453 __IO uint32_t PTPTSLUR;
454 __IO uint32_t PTPTSAR;
455 __IO uint32_t PTPTTHR;
456 __IO uint32_t PTPTTLR;
457 __IO uint32_t RESERVED8;
458 __IO uint32_t PTPTSSR;
459 uint32_t RESERVED9[565];
460 __IO uint32_t DMABMR;
461 __IO uint32_t DMATPDR;
462 __IO uint32_t DMARPDR;
463 __IO uint32_t DMARDLAR;
464 __IO uint32_t DMATDLAR;
465 __IO uint32_t DMASR;
466 __IO uint32_t DMAOMR;
467 __IO uint32_t DMAIER;
468 __IO uint32_t DMAMFBOCR;
469 __IO uint32_t DMARSWTR;
470 uint32_t RESERVED10[8];
471 __IO uint32_t DMACHTDR;
472 __IO uint32_t DMACHRDR;
473 __IO uint32_t DMACHTBAR;
474 __IO uint32_t DMACHRBAR;
475} ETH_TypeDef;
476
480
481typedef struct
482{
483 __IO uint32_t IMR;
484 __IO uint32_t EMR;
485 __IO uint32_t RTSR;
486 __IO uint32_t FTSR;
487 __IO uint32_t SWIER;
488 __IO uint32_t PR;
489} EXTI_TypeDef;
490
494
495typedef struct
496{
497 __IO uint32_t ACR;
498 __IO uint32_t KEYR;
499 __IO uint32_t OPTKEYR;
500 __IO uint32_t SR;
501 __IO uint32_t CR;
502 __IO uint32_t OPTCR;
503 __IO uint32_t OPTCR1;
504} FLASH_TypeDef;
505
509
510typedef struct
511{
512 __IO uint32_t BTCR[8];
513} FMC_Bank1_TypeDef;
514
518
519typedef struct
520{
521 __IO uint32_t BWTR[7];
522} FMC_Bank1E_TypeDef;
526
527typedef struct
528{
529 __IO uint32_t PCR2;
530 __IO uint32_t SR2;
531 __IO uint32_t PMEM2;
532 __IO uint32_t PATT2;
533 uint32_t RESERVED0;
534 __IO uint32_t ECCR2;
535 uint32_t RESERVED1;
536 uint32_t RESERVED2;
537 __IO uint32_t PCR3;
538 __IO uint32_t SR3;
539 __IO uint32_t PMEM3;
540 __IO uint32_t PATT3;
541 uint32_t RESERVED3;
542 __IO uint32_t ECCR3;
543} FMC_Bank2_3_TypeDef;
544
548
549typedef struct
550{
551 __IO uint32_t PCR4;
552 __IO uint32_t SR4;
553 __IO uint32_t PMEM4;
554 __IO uint32_t PATT4;
555 __IO uint32_t PIO4;
556} FMC_Bank4_TypeDef;
557
561
562typedef struct
563{
564 __IO uint32_t SDCR[2];
565 __IO uint32_t SDTR[2];
566 __IO uint32_t SDCMR;
567 __IO uint32_t SDRTR;
568 __IO uint32_t SDSR;
569} FMC_Bank5_6_TypeDef;
570
574
575typedef struct
576{
577 __IO uint32_t MODER;
578 __IO uint32_t OTYPER;
579 __IO uint32_t OSPEEDR;
580 __IO uint32_t PUPDR;
581 __IO uint32_t IDR;
582 __IO uint32_t ODR;
583 __IO uint32_t BSRR;
584 __IO uint32_t LCKR;
585 __IO uint32_t AFR[2];
586} GPIO_TypeDef;
587
591
592typedef struct
593{
594 __IO uint32_t MEMRMP;
595 __IO uint32_t PMC;
596 __IO uint32_t EXTICR[4];
597 uint32_t RESERVED[2];
598 __IO uint32_t CMPCR;
599} SYSCFG_TypeDef;
600
604
605typedef struct
606{
607 __IO uint32_t CR1;
608 __IO uint32_t CR2;
609 __IO uint32_t OAR1;
610 __IO uint32_t OAR2;
611 __IO uint32_t DR;
612 __IO uint32_t SR1;
613 __IO uint32_t SR2;
614 __IO uint32_t CCR;
615 __IO uint32_t TRISE;
616 __IO uint32_t FLTR;
617} I2C_TypeDef;
618
622
623typedef struct
624{
625 __IO uint32_t KR;
626 __IO uint32_t PR;
627 __IO uint32_t RLR;
628 __IO uint32_t SR;
629} IWDG_TypeDef;
630
634
635typedef struct
636{
637 uint32_t RESERVED0[2];
638 __IO uint32_t SSCR;
639 __IO uint32_t BPCR;
640 __IO uint32_t AWCR;
641 __IO uint32_t TWCR;
642 __IO uint32_t GCR;
643 uint32_t RESERVED1[2];
644 __IO uint32_t SRCR;
645 uint32_t RESERVED2[1];
646 __IO uint32_t BCCR;
647 uint32_t RESERVED3[1];
648 __IO uint32_t IER;
649 __IO uint32_t ISR;
650 __IO uint32_t ICR;
651 __IO uint32_t LIPCR;
652 __IO uint32_t CPSR;
653 __IO uint32_t CDSR;
654} LTDC_TypeDef;
655
659
660typedef struct
661{
662 __IO uint32_t CR;
663 __IO uint32_t WHPCR;
664 __IO uint32_t WVPCR;
665 __IO uint32_t CKCR;
666 __IO uint32_t PFCR;
667 __IO uint32_t CACR;
668 __IO uint32_t DCCR;
669 __IO uint32_t BFCR;
670 uint32_t RESERVED0[2];
671 __IO uint32_t CFBAR;
672 __IO uint32_t CFBLR;
673 __IO uint32_t CFBLNR;
674 uint32_t RESERVED1[3];
675 __IO uint32_t CLUTWR;
676} LTDC_Layer_TypeDef;
677
681
682typedef struct
683{
684 __IO uint32_t CR;
685 __IO uint32_t CSR;
686} PWR_TypeDef;
687
691
692typedef struct
693{
694 __IO uint32_t CR;
695 __IO uint32_t PLLCFGR;
696 __IO uint32_t CFGR;
697 __IO uint32_t CIR;
698 __IO uint32_t AHB1RSTR;
699 __IO uint32_t AHB2RSTR;
700 __IO uint32_t AHB3RSTR;
701 uint32_t RESERVED0;
702 __IO uint32_t APB1RSTR;
703 __IO uint32_t APB2RSTR;
704 uint32_t RESERVED1[2];
705 __IO uint32_t AHB1ENR;
706 __IO uint32_t AHB2ENR;
707 __IO uint32_t AHB3ENR;
708 uint32_t RESERVED2;
709 __IO uint32_t APB1ENR;
710 __IO uint32_t APB2ENR;
711 uint32_t RESERVED3[2];
712 __IO uint32_t AHB1LPENR;
713 __IO uint32_t AHB2LPENR;
714 __IO uint32_t AHB3LPENR;
715 uint32_t RESERVED4;
716 __IO uint32_t APB1LPENR;
717 __IO uint32_t APB2LPENR;
718 uint32_t RESERVED5[2];
719 __IO uint32_t BDCR;
720 __IO uint32_t CSR;
721 uint32_t RESERVED6[2];
722 __IO uint32_t SSCGR;
723 __IO uint32_t PLLI2SCFGR;
724 __IO uint32_t PLLSAICFGR;
725 __IO uint32_t DCKCFGR;
726} RCC_TypeDef;
727
731
732typedef struct
733{
734 __IO uint32_t TR;
735 __IO uint32_t DR;
736 __IO uint32_t CR;
737 __IO uint32_t ISR;
738 __IO uint32_t PRER;
739 __IO uint32_t WUTR;
740 __IO uint32_t CALIBR;
741 __IO uint32_t ALRMAR;
742 __IO uint32_t ALRMBR;
743 __IO uint32_t WPR;
744 __IO uint32_t SSR;
745 __IO uint32_t SHIFTR;
746 __IO uint32_t TSTR;
747 __IO uint32_t TSDR;
748 __IO uint32_t TSSSR;
749 __IO uint32_t CALR;
750 __IO uint32_t TAFCR;
751 __IO uint32_t ALRMASSR;
752 __IO uint32_t ALRMBSSR;
753 uint32_t RESERVED7;
754 __IO uint32_t BKP0R;
755 __IO uint32_t BKP1R;
756 __IO uint32_t BKP2R;
757 __IO uint32_t BKP3R;
758 __IO uint32_t BKP4R;
759 __IO uint32_t BKP5R;
760 __IO uint32_t BKP6R;
761 __IO uint32_t BKP7R;
762 __IO uint32_t BKP8R;
763 __IO uint32_t BKP9R;
764 __IO uint32_t BKP10R;
765 __IO uint32_t BKP11R;
766 __IO uint32_t BKP12R;
767 __IO uint32_t BKP13R;
768 __IO uint32_t BKP14R;
769 __IO uint32_t BKP15R;
770 __IO uint32_t BKP16R;
771 __IO uint32_t BKP17R;
772 __IO uint32_t BKP18R;
773 __IO uint32_t BKP19R;
774} RTC_TypeDef;
775
779
780typedef struct
781{
782 __IO uint32_t GCR;
783} SAI_TypeDef;
784
785typedef struct
786{
787 __IO uint32_t CR1;
788 __IO uint32_t CR2;
789 __IO uint32_t FRCR;
790 __IO uint32_t SLOTR;
791 __IO uint32_t IMR;
792 __IO uint32_t SR;
793 __IO uint32_t CLRFR;
794 __IO uint32_t DR;
795} SAI_Block_TypeDef;
796
800
801typedef struct
802{
803 __IO uint32_t POWER;
804 __IO uint32_t CLKCR;
805 __IO uint32_t ARG;
806 __IO uint32_t CMD;
807 __IO const uint32_t RESPCMD;
808 __IO const uint32_t RESP1;
809 __IO const uint32_t RESP2;
810 __IO const uint32_t RESP3;
811 __IO const uint32_t RESP4;
812 __IO uint32_t DTIMER;
813 __IO uint32_t DLEN;
814 __IO uint32_t DCTRL;
815 __IO const uint32_t DCOUNT;
816 __IO const uint32_t STA;
817 __IO uint32_t ICR;
818 __IO uint32_t MASK;
819 uint32_t RESERVED0[2];
820 __IO const uint32_t FIFOCNT;
821 uint32_t RESERVED1[13];
822 __IO uint32_t FIFO;
823} SDIO_TypeDef;
824
828
829typedef struct
830{
831 __IO uint32_t CR1;
832 __IO uint32_t CR2;
833 __IO uint32_t SR;
834 __IO uint32_t DR;
835 __IO uint32_t CRCPR;
836 __IO uint32_t RXCRCR;
837 __IO uint32_t TXCRCR;
838 __IO uint32_t I2SCFGR;
839 __IO uint32_t I2SPR;
840} SPI_TypeDef;
841
842
846
847typedef struct
848{
849 __IO uint32_t CR1;
850 __IO uint32_t CR2;
851 __IO uint32_t SMCR;
852 __IO uint32_t DIER;
853 __IO uint32_t SR;
854 __IO uint32_t EGR;
855 __IO uint32_t CCMR1;
856 __IO uint32_t CCMR2;
857 __IO uint32_t CCER;
858 __IO uint32_t CNT;
859 __IO uint32_t PSC;
860 __IO uint32_t ARR;
861 __IO uint32_t RCR;
862 __IO uint32_t CCR1;
863 __IO uint32_t CCR2;
864 __IO uint32_t CCR3;
865 __IO uint32_t CCR4;
866 __IO uint32_t BDTR;
867 __IO uint32_t DCR;
868 __IO uint32_t DMAR;
869 __IO uint32_t OR;
870} TIM_TypeDef;
871
875
876typedef struct
877{
878 __IO uint32_t SR;
879 __IO uint32_t DR;
880 __IO uint32_t BRR;
881 __IO uint32_t CR1;
882 __IO uint32_t CR2;
883 __IO uint32_t CR3;
884 __IO uint32_t GTPR;
885} USART_TypeDef;
886
890
891typedef struct
892{
893 __IO uint32_t CR;
894 __IO uint32_t CFR;
895 __IO uint32_t SR;
896} WWDG_TypeDef;
897
901
902typedef struct
903{
904 __IO uint32_t CR;
905 __IO uint32_t SR;
906 __IO uint32_t DIN;
907 __IO uint32_t DOUT;
908 __IO uint32_t DMACR;
909 __IO uint32_t IMSCR;
910 __IO uint32_t RISR;
911 __IO uint32_t MISR;
912 __IO uint32_t K0LR;
913 __IO uint32_t K0RR;
914 __IO uint32_t K1LR;
915 __IO uint32_t K1RR;
916 __IO uint32_t K2LR;
917 __IO uint32_t K2RR;
918 __IO uint32_t K3LR;
919 __IO uint32_t K3RR;
920 __IO uint32_t IV0LR;
921 __IO uint32_t IV0RR;
922 __IO uint32_t IV1LR;
923 __IO uint32_t IV1RR;
924 __IO uint32_t CSGCMCCM0R;
925 __IO uint32_t CSGCMCCM1R;
926 __IO uint32_t CSGCMCCM2R;
927 __IO uint32_t CSGCMCCM3R;
928 __IO uint32_t CSGCMCCM4R;
929 __IO uint32_t CSGCMCCM5R;
930 __IO uint32_t CSGCMCCM6R;
931 __IO uint32_t CSGCMCCM7R;
932 __IO uint32_t CSGCM0R;
933 __IO uint32_t CSGCM1R;
934 __IO uint32_t CSGCM2R;
935 __IO uint32_t CSGCM3R;
936 __IO uint32_t CSGCM4R;
937 __IO uint32_t CSGCM5R;
938 __IO uint32_t CSGCM6R;
939 __IO uint32_t CSGCM7R;
940} CRYP_TypeDef;
941
945
946typedef struct
947{
948 __IO uint32_t CR;
949 __IO uint32_t DIN;
950 __IO uint32_t STR;
951 __IO uint32_t HR[5];
952 __IO uint32_t IMR;
953 __IO uint32_t SR;
954 uint32_t RESERVED[52];
955 __IO uint32_t CSR[54];
956} HASH_TypeDef;
957
961
962typedef struct
963{
964 __IO uint32_t HR[8];
965} HASH_DIGEST_TypeDef;
966
970
971typedef struct
972{
973 __IO uint32_t CR;
974 __IO uint32_t SR;
975 __IO uint32_t DR;
976} RNG_TypeDef;
977
981typedef struct
982{
983 __IO uint32_t GOTGCTL;
984 __IO uint32_t GOTGINT;
985 __IO uint32_t GAHBCFG;
986 __IO uint32_t GUSBCFG;
987 __IO uint32_t GRSTCTL;
988 __IO uint32_t GINTSTS;
989 __IO uint32_t GINTMSK;
990 __IO uint32_t GRXSTSR;
991 __IO uint32_t GRXSTSP;
992 __IO uint32_t GRXFSIZ;
993 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
994 __IO uint32_t HNPTXSTS;
995 uint32_t Reserved30[2];
996 __IO uint32_t GCCFG;
997 __IO uint32_t CID;
998 uint32_t Reserved40[48];
999 __IO uint32_t HPTXFSIZ;
1000 __IO uint32_t DIEPTXF[0x0F];
1001} USB_OTG_GlobalTypeDef;
1002
1006typedef struct
1007{
1008 __IO uint32_t DCFG;
1009 __IO uint32_t DCTL;
1010 __IO uint32_t DSTS;
1011 uint32_t Reserved0C;
1012 __IO uint32_t DIEPMSK;
1013 __IO uint32_t DOEPMSK;
1014 __IO uint32_t DAINT;
1015 __IO uint32_t DAINTMSK;
1016 uint32_t Reserved20;
1017 uint32_t Reserved9;
1018 __IO uint32_t DVBUSDIS;
1019 __IO uint32_t DVBUSPULSE;
1020 __IO uint32_t DTHRCTL;
1021 __IO uint32_t DIEPEMPMSK;
1022 __IO uint32_t DEACHINT;
1023 __IO uint32_t DEACHMSK;
1024 uint32_t Reserved40;
1025 __IO uint32_t DINEP1MSK;
1026 uint32_t Reserved44[15];
1027 __IO uint32_t DOUTEP1MSK;
1028} USB_OTG_DeviceTypeDef;
1029
1033typedef struct
1034{
1035 __IO uint32_t DIEPCTL;
1036 uint32_t Reserved04;
1037 __IO uint32_t DIEPINT;
1038 uint32_t Reserved0C;
1039 __IO uint32_t DIEPTSIZ;
1040 __IO uint32_t DIEPDMA;
1041 __IO uint32_t DTXFSTS;
1042 uint32_t Reserved18;
1043} USB_OTG_INEndpointTypeDef;
1044
1048typedef struct
1049{
1050 __IO uint32_t DOEPCTL;
1051 uint32_t Reserved04;
1052 __IO uint32_t DOEPINT;
1053 uint32_t Reserved0C;
1054 __IO uint32_t DOEPTSIZ;
1055 __IO uint32_t DOEPDMA;
1056 uint32_t Reserved18[2];
1057} USB_OTG_OUTEndpointTypeDef;
1058
1062typedef struct
1063{
1064 __IO uint32_t HCFG;
1065 __IO uint32_t HFIR;
1066 __IO uint32_t HFNUM;
1067 uint32_t Reserved40C;
1068 __IO uint32_t HPTXSTS;
1069 __IO uint32_t HAINT;
1070 __IO uint32_t HAINTMSK;
1071} USB_OTG_HostTypeDef;
1072
1076typedef struct
1077{
1078 __IO uint32_t HCCHAR;
1079 __IO uint32_t HCSPLT;
1080 __IO uint32_t HCINT;
1081 __IO uint32_t HCINTMSK;
1082 __IO uint32_t HCTSIZ;
1083 __IO uint32_t HCDMA;
1084 uint32_t Reserved[2];
1085} USB_OTG_HostChannelTypeDef;
1086
1090
1094#define FLASH_BASE 0x08000000UL
1095#define CCMDATARAM_BASE 0x10000000UL
1096#define SRAM1_BASE 0x20000000UL
1097#define SRAM2_BASE 0x2001C000UL
1098#define SRAM3_BASE 0x20020000UL
1099#define PERIPH_BASE 0x40000000UL
1100#define BKPSRAM_BASE 0x40024000UL
1101#define FMC_R_BASE 0xA0000000UL
1102#define SRAM1_BB_BASE 0x22000000UL
1103#define SRAM2_BB_BASE 0x22380000UL
1104#define SRAM3_BB_BASE 0x22400000UL
1105#define PERIPH_BB_BASE 0x42000000UL
1106#define BKPSRAM_BB_BASE 0x42480000UL
1107#define FLASH_END 0x081FFFFFUL
1108#define FLASH_OTP_BASE 0x1FFF7800UL
1109#define FLASH_OTP_END 0x1FFF7A0FUL
1110#define CCMDATARAM_END 0x1000FFFFUL
1111
1112/* Legacy defines */
1113#define SRAM_BASE SRAM1_BASE
1114#define SRAM_BB_BASE SRAM1_BB_BASE
1115
1117#define APB1PERIPH_BASE PERIPH_BASE
1118#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
1119#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
1120#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
1121
1123#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
1124#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
1125#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
1126#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
1127#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
1128#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
1129#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
1130#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
1131#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
1132#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
1133#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
1134#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
1135#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
1136#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
1137#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
1138#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
1139#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
1140#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
1141#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
1142#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
1143#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
1144#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
1145#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
1146#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
1147#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
1148#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
1149#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
1150#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)
1151#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)
1152
1154#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
1155#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
1156#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
1157#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
1158#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
1159#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
1160#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
1161#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
1162/* Legacy define */
1163#define ADC_BASE ADC123_COMMON_BASE
1164#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
1165#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
1166#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
1167#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
1168#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
1169#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
1170#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
1171#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
1172#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
1173#define SPI6_BASE (APB2PERIPH_BASE + 0x5400UL)
1174#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
1175#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
1176#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
1177#define LTDC_BASE (APB2PERIPH_BASE + 0x6800UL)
1178#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
1179#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
1180
1182#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
1183#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
1184#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
1185#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
1186#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
1187#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
1188#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
1189#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
1190#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
1191#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400UL)
1192#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800UL)
1193#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
1194#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
1195#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
1196#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
1197#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
1198#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
1199#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
1200#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
1201#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
1202#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
1203#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
1204#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
1205#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
1206#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
1207#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
1208#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
1209#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
1210#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
1211#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
1212#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
1213#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
1214#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL)
1215#define ETH_MAC_BASE (ETH_BASE)
1216#define ETH_MMC_BASE (ETH_BASE + 0x0100UL)
1217#define ETH_PTP_BASE (ETH_BASE + 0x0700UL)
1218#define ETH_DMA_BASE (ETH_BASE + 0x1000UL)
1219#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL)
1220
1222#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)
1223#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000UL)
1224#define HASH_BASE (AHB2PERIPH_BASE + 0x60400UL)
1225#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710UL)
1226#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
1227
1229#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
1230#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
1231#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060UL)
1232#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0UL)
1233#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
1234
1235
1237#define DBGMCU_BASE 0xE0042000UL
1239#define USB_OTG_HS_PERIPH_BASE 0x40040000UL
1240#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
1241
1242#define USB_OTG_GLOBAL_BASE 0x000UL
1243#define USB_OTG_DEVICE_BASE 0x800UL
1244#define USB_OTG_IN_ENDPOINT_BASE 0x900UL
1245#define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
1246#define USB_OTG_EP_REG_SIZE 0x20UL
1247#define USB_OTG_HOST_BASE 0x400UL
1248#define USB_OTG_HOST_PORT_BASE 0x440UL
1249#define USB_OTG_HOST_CHANNEL_BASE 0x500UL
1250#define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
1251#define USB_OTG_PCGCCTL_BASE 0xE00UL
1252#define USB_OTG_FIFO_BASE 0x1000UL
1253#define USB_OTG_FIFO_SIZE 0x1000UL
1254
1255#define UID_BASE 0x1FFF7A10UL
1256#define FLASHSIZE_BASE 0x1FFF7A22UL
1257#define PACKAGE_BASE 0x1FFF7BF0UL
1261
1265#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1266#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1267#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1268#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1269#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1270#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1271#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1272#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1273#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1274#define RTC ((RTC_TypeDef *) RTC_BASE)
1275#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1276#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1277#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1278#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1279#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1280#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1281#define USART2 ((USART_TypeDef *) USART2_BASE)
1282#define USART3 ((USART_TypeDef *) USART3_BASE)
1283#define UART4 ((USART_TypeDef *) UART4_BASE)
1284#define UART5 ((USART_TypeDef *) UART5_BASE)
1285#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1286#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1287#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1288#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1289#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1290#define PWR ((PWR_TypeDef *) PWR_BASE)
1291#define DAC1 ((DAC_TypeDef *) DAC_BASE)
1292#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1293#define UART7 ((USART_TypeDef *) UART7_BASE)
1294#define UART8 ((USART_TypeDef *) UART8_BASE)
1295#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1296#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1297#define USART1 ((USART_TypeDef *) USART1_BASE)
1298#define USART6 ((USART_TypeDef *) USART6_BASE)
1299#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1300#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1301#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1302#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1303/* Legacy define */
1304#define ADC ADC123_COMMON
1305#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1306#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1307#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1308#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1309#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1310#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1311#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1312#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1313#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1314#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1315#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1316#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1317#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1318#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1319#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1320#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1321#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1322#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1323#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1324#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1325#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1326#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1327#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1328#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1329#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1330#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1331#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1332#define CRC ((CRC_TypeDef *) CRC_BASE)
1333#define RCC ((RCC_TypeDef *) RCC_BASE)
1334#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1335#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1336#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1337#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1338#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1339#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1340#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1341#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1342#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1343#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1344#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1345#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1346#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1347#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1348#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1349#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1350#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1351#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1352#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1353#define ETH ((ETH_TypeDef *) ETH_BASE)
1354#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1355#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1356#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
1357#define HASH ((HASH_TypeDef *) HASH_BASE)
1358#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1359#define RNG ((RNG_TypeDef *) RNG_BASE)
1360#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1361#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1362#define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
1363#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
1364#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1365#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1366#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1367#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1368
1372
1376
1380#define LSI_STARTUP_TIME 40U
1384
1388
1389/******************************************************************************/
1390/* Peripheral Registers_Bits_Definition */
1391/******************************************************************************/
1392
1393/******************************************************************************/
1394/* */
1395/* Analog to Digital Converter */
1396/* */
1397/******************************************************************************/
1398/*
1399 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
1400 */
1401#define ADC_MULTIMODE_SUPPORT
1402
1403/******************** Bit definition for ADC_SR register ********************/
1404#define ADC_SR_AWD_Pos (0U)
1405#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
1406#define ADC_SR_AWD ADC_SR_AWD_Msk
1407#define ADC_SR_EOC_Pos (1U)
1408#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
1409#define ADC_SR_EOC ADC_SR_EOC_Msk
1410#define ADC_SR_JEOC_Pos (2U)
1411#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
1412#define ADC_SR_JEOC ADC_SR_JEOC_Msk
1413#define ADC_SR_JSTRT_Pos (3U)
1414#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
1415#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
1416#define ADC_SR_STRT_Pos (4U)
1417#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
1418#define ADC_SR_STRT ADC_SR_STRT_Msk
1419#define ADC_SR_OVR_Pos (5U)
1420#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
1421#define ADC_SR_OVR ADC_SR_OVR_Msk
1422
1423/******************* Bit definition for ADC_CR1 register ********************/
1424#define ADC_CR1_AWDCH_Pos (0U)
1425#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
1426#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
1427#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
1428#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
1429#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
1430#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
1431#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
1432#define ADC_CR1_EOCIE_Pos (5U)
1433#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
1434#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
1435#define ADC_CR1_AWDIE_Pos (6U)
1436#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
1437#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
1438#define ADC_CR1_JEOCIE_Pos (7U)
1439#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
1440#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
1441#define ADC_CR1_SCAN_Pos (8U)
1442#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
1443#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
1444#define ADC_CR1_AWDSGL_Pos (9U)
1445#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
1446#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
1447#define ADC_CR1_JAUTO_Pos (10U)
1448#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
1449#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
1450#define ADC_CR1_DISCEN_Pos (11U)
1451#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
1452#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
1453#define ADC_CR1_JDISCEN_Pos (12U)
1454#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
1455#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
1456#define ADC_CR1_DISCNUM_Pos (13U)
1457#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
1458#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
1459#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
1460#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
1461#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
1462#define ADC_CR1_JAWDEN_Pos (22U)
1463#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
1464#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
1465#define ADC_CR1_AWDEN_Pos (23U)
1466#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
1467#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
1468#define ADC_CR1_RES_Pos (24U)
1469#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
1470#define ADC_CR1_RES ADC_CR1_RES_Msk
1471#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
1472#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
1473#define ADC_CR1_OVRIE_Pos (26U)
1474#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
1475#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
1476
1477/******************* Bit definition for ADC_CR2 register ********************/
1478#define ADC_CR2_ADON_Pos (0U)
1479#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
1480#define ADC_CR2_ADON ADC_CR2_ADON_Msk
1481#define ADC_CR2_CONT_Pos (1U)
1482#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
1483#define ADC_CR2_CONT ADC_CR2_CONT_Msk
1484#define ADC_CR2_DMA_Pos (8U)
1485#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
1486#define ADC_CR2_DMA ADC_CR2_DMA_Msk
1487#define ADC_CR2_DDS_Pos (9U)
1488#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
1489#define ADC_CR2_DDS ADC_CR2_DDS_Msk
1490#define ADC_CR2_EOCS_Pos (10U)
1491#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
1492#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk
1493#define ADC_CR2_ALIGN_Pos (11U)
1494#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
1495#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
1496#define ADC_CR2_JEXTSEL_Pos (16U)
1497#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
1498#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
1499#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
1500#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
1501#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
1502#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
1503#define ADC_CR2_JEXTEN_Pos (20U)
1504#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
1505#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
1506#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
1507#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
1508#define ADC_CR2_JSWSTART_Pos (22U)
1509#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
1510#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
1511#define ADC_CR2_EXTSEL_Pos (24U)
1512#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
1513#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
1514#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
1515#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
1516#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
1517#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
1518#define ADC_CR2_EXTEN_Pos (28U)
1519#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
1520#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
1521#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
1522#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
1523#define ADC_CR2_SWSTART_Pos (30U)
1524#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
1525#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
1526
1527/****************** Bit definition for ADC_SMPR1 register *******************/
1528#define ADC_SMPR1_SMP10_Pos (0U)
1529#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
1530#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
1531#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
1532#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
1533#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
1534#define ADC_SMPR1_SMP11_Pos (3U)
1535#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
1536#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
1537#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
1538#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
1539#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
1540#define ADC_SMPR1_SMP12_Pos (6U)
1541#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
1542#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
1543#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
1544#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
1545#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
1546#define ADC_SMPR1_SMP13_Pos (9U)
1547#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
1548#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
1549#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
1550#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
1551#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
1552#define ADC_SMPR1_SMP14_Pos (12U)
1553#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
1554#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
1555#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
1556#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
1557#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
1558#define ADC_SMPR1_SMP15_Pos (15U)
1559#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
1560#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
1561#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
1562#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
1563#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
1564#define ADC_SMPR1_SMP16_Pos (18U)
1565#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
1566#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
1567#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
1568#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
1569#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
1570#define ADC_SMPR1_SMP17_Pos (21U)
1571#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
1572#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
1573#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
1574#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
1575#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
1576#define ADC_SMPR1_SMP18_Pos (24U)
1577#define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
1578#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk
1579#define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)
1580#define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)
1581#define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)
1582
1583/****************** Bit definition for ADC_SMPR2 register *******************/
1584#define ADC_SMPR2_SMP0_Pos (0U)
1585#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
1586#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
1587#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
1588#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
1589#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
1590#define ADC_SMPR2_SMP1_Pos (3U)
1591#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
1592#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
1593#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
1594#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
1595#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
1596#define ADC_SMPR2_SMP2_Pos (6U)
1597#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
1598#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
1599#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
1600#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
1601#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
1602#define ADC_SMPR2_SMP3_Pos (9U)
1603#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
1604#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
1605#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
1606#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
1607#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
1608#define ADC_SMPR2_SMP4_Pos (12U)
1609#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
1610#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
1611#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
1612#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
1613#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
1614#define ADC_SMPR2_SMP5_Pos (15U)
1615#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
1616#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
1617#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
1618#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
1619#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
1620#define ADC_SMPR2_SMP6_Pos (18U)
1621#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
1622#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
1623#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
1624#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
1625#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
1626#define ADC_SMPR2_SMP7_Pos (21U)
1627#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
1628#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
1629#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
1630#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
1631#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
1632#define ADC_SMPR2_SMP8_Pos (24U)
1633#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
1634#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
1635#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
1636#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
1637#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
1638#define ADC_SMPR2_SMP9_Pos (27U)
1639#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
1640#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
1641#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
1642#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
1643#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
1644
1645/****************** Bit definition for ADC_JOFR1 register *******************/
1646#define ADC_JOFR1_JOFFSET1_Pos (0U)
1647#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
1648#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
1649
1650/****************** Bit definition for ADC_JOFR2 register *******************/
1651#define ADC_JOFR2_JOFFSET2_Pos (0U)
1652#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
1653#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
1654
1655/****************** Bit definition for ADC_JOFR3 register *******************/
1656#define ADC_JOFR3_JOFFSET3_Pos (0U)
1657#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
1658#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
1659
1660/****************** Bit definition for ADC_JOFR4 register *******************/
1661#define ADC_JOFR4_JOFFSET4_Pos (0U)
1662#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
1663#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
1664
1665/******************* Bit definition for ADC_HTR register ********************/
1666#define ADC_HTR_HT_Pos (0U)
1667#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
1668#define ADC_HTR_HT ADC_HTR_HT_Msk
1669
1670/******************* Bit definition for ADC_LTR register ********************/
1671#define ADC_LTR_LT_Pos (0U)
1672#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
1673#define ADC_LTR_LT ADC_LTR_LT_Msk
1674
1675/******************* Bit definition for ADC_SQR1 register *******************/
1676#define ADC_SQR1_SQ13_Pos (0U)
1677#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
1678#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
1679#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
1680#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
1681#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
1682#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
1683#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
1684#define ADC_SQR1_SQ14_Pos (5U)
1685#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
1686#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
1687#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
1688#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
1689#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
1690#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
1691#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
1692#define ADC_SQR1_SQ15_Pos (10U)
1693#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
1694#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
1695#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
1696#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
1697#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
1698#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
1699#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
1700#define ADC_SQR1_SQ16_Pos (15U)
1701#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
1702#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
1703#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
1704#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
1705#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
1706#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
1707#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
1708#define ADC_SQR1_L_Pos (20U)
1709#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1710#define ADC_SQR1_L ADC_SQR1_L_Msk
1711#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1712#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1713#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1714#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1715
1716/******************* Bit definition for ADC_SQR2 register *******************/
1717#define ADC_SQR2_SQ7_Pos (0U)
1718#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1719#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1720#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1721#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1722#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1723#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1724#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1725#define ADC_SQR2_SQ8_Pos (5U)
1726#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
1727#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
1728#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
1729#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
1730#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
1731#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
1732#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
1733#define ADC_SQR2_SQ9_Pos (10U)
1734#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
1735#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
1736#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
1737#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
1738#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
1739#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
1740#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
1741#define ADC_SQR2_SQ10_Pos (15U)
1742#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
1743#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
1744#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
1745#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
1746#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
1747#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
1748#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
1749#define ADC_SQR2_SQ11_Pos (20U)
1750#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
1751#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
1752#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
1753#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
1754#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
1755#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
1756#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
1757#define ADC_SQR2_SQ12_Pos (25U)
1758#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
1759#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
1760#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
1761#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
1762#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
1763#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
1764#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
1765
1766/******************* Bit definition for ADC_SQR3 register *******************/
1767#define ADC_SQR3_SQ1_Pos (0U)
1768#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
1769#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
1770#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
1771#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
1772#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
1773#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
1774#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
1775#define ADC_SQR3_SQ2_Pos (5U)
1776#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
1777#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
1778#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
1779#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
1780#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
1781#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
1782#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
1783#define ADC_SQR3_SQ3_Pos (10U)
1784#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
1785#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
1786#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
1787#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
1788#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
1789#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
1790#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
1791#define ADC_SQR3_SQ4_Pos (15U)
1792#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
1793#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
1794#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
1795#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
1796#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
1797#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
1798#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
1799#define ADC_SQR3_SQ5_Pos (20U)
1800#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
1801#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
1802#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
1803#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
1804#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
1805#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
1806#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
1807#define ADC_SQR3_SQ6_Pos (25U)
1808#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
1809#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
1810#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
1811#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
1812#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
1813#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
1814#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
1815
1816/******************* Bit definition for ADC_JSQR register *******************/
1817#define ADC_JSQR_JSQ1_Pos (0U)
1818#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
1819#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
1820#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
1821#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
1822#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
1823#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
1824#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
1825#define ADC_JSQR_JSQ2_Pos (5U)
1826#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
1827#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
1828#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
1829#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
1830#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
1831#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
1832#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
1833#define ADC_JSQR_JSQ3_Pos (10U)
1834#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
1835#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
1836#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
1837#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
1838#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
1839#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
1840#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
1841#define ADC_JSQR_JSQ4_Pos (15U)
1842#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
1843#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
1844#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
1845#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
1846#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
1847#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
1848#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
1849#define ADC_JSQR_JL_Pos (20U)
1850#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
1851#define ADC_JSQR_JL ADC_JSQR_JL_Msk
1852#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
1853#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
1854
1855/******************* Bit definition for ADC_JDR1 register *******************/
1856#define ADC_JDR1_JDATA_Pos (0U)
1857#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
1858#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
1859
1860/******************* Bit definition for ADC_JDR2 register *******************/
1861#define ADC_JDR2_JDATA_Pos (0U)
1862#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
1863#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
1864
1865/******************* Bit definition for ADC_JDR3 register *******************/
1866#define ADC_JDR3_JDATA_Pos (0U)
1867#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
1868#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
1869
1870/******************* Bit definition for ADC_JDR4 register *******************/
1871#define ADC_JDR4_JDATA_Pos (0U)
1872#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
1873#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
1874
1875/******************** Bit definition for ADC_DR register ********************/
1876#define ADC_DR_DATA_Pos (0U)
1877#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
1878#define ADC_DR_DATA ADC_DR_DATA_Msk
1879#define ADC_DR_ADC2DATA_Pos (16U)
1880#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
1881#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
1882
1883/******************* Bit definition for ADC_CSR register ********************/
1884#define ADC_CSR_AWD1_Pos (0U)
1885#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)
1886#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk
1887#define ADC_CSR_EOC1_Pos (1U)
1888#define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)
1889#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk
1890#define ADC_CSR_JEOC1_Pos (2U)
1891#define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)
1892#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk
1893#define ADC_CSR_JSTRT1_Pos (3U)
1894#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)
1895#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk
1896#define ADC_CSR_STRT1_Pos (4U)
1897#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)
1898#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk
1899#define ADC_CSR_OVR1_Pos (5U)
1900#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)
1901#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk
1902#define ADC_CSR_AWD2_Pos (8U)
1903#define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos)
1904#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk
1905#define ADC_CSR_EOC2_Pos (9U)
1906#define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos)
1907#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk
1908#define ADC_CSR_JEOC2_Pos (10U)
1909#define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos)
1910#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk
1911#define ADC_CSR_JSTRT2_Pos (11U)
1912#define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos)
1913#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk
1914#define ADC_CSR_STRT2_Pos (12U)
1915#define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos)
1916#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk
1917#define ADC_CSR_OVR2_Pos (13U)
1918#define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos)
1919#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk
1920#define ADC_CSR_AWD3_Pos (16U)
1921#define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos)
1922#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk
1923#define ADC_CSR_EOC3_Pos (17U)
1924#define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos)
1925#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk
1926#define ADC_CSR_JEOC3_Pos (18U)
1927#define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos)
1928#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk
1929#define ADC_CSR_JSTRT3_Pos (19U)
1930#define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos)
1931#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk
1932#define ADC_CSR_STRT3_Pos (20U)
1933#define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos)
1934#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk
1935#define ADC_CSR_OVR3_Pos (21U)
1936#define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos)
1937#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk
1938
1939/* Legacy defines */
1940#define ADC_CSR_DOVR1 ADC_CSR_OVR1
1941#define ADC_CSR_DOVR2 ADC_CSR_OVR2
1942#define ADC_CSR_DOVR3 ADC_CSR_OVR3
1943
1944/******************* Bit definition for ADC_CCR register ********************/
1945#define ADC_CCR_MULTI_Pos (0U)
1946#define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)
1947#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk
1948#define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)
1949#define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)
1950#define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)
1951#define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)
1952#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)
1953#define ADC_CCR_DELAY_Pos (8U)
1954#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
1955#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
1956#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
1957#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
1958#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
1959#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
1960#define ADC_CCR_DDS_Pos (13U)
1961#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)
1962#define ADC_CCR_DDS ADC_CCR_DDS_Msk
1963#define ADC_CCR_DMA_Pos (14U)
1964#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)
1965#define ADC_CCR_DMA ADC_CCR_DMA_Msk
1966#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)
1967#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)
1968#define ADC_CCR_ADCPRE_Pos (16U)
1969#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)
1970#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk
1971#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)
1972#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)
1973#define ADC_CCR_VBATE_Pos (22U)
1974#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)
1975#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk
1976#define ADC_CCR_TSVREFE_Pos (23U)
1977#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)
1978#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk
1979
1980/******************* Bit definition for ADC_CDR register ********************/
1981#define ADC_CDR_DATA1_Pos (0U)
1982#define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)
1983#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk
1984#define ADC_CDR_DATA2_Pos (16U)
1985#define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)
1986#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk
1987
1988/* Legacy defines */
1989#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1990#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1991
1992/******************************************************************************/
1993/* */
1994/* Controller Area Network */
1995/* */
1996/******************************************************************************/
1998/******************* Bit definition for CAN_MCR register ********************/
1999#define CAN_MCR_INRQ_Pos (0U)
2000#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
2001#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
2002#define CAN_MCR_SLEEP_Pos (1U)
2003#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
2004#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
2005#define CAN_MCR_TXFP_Pos (2U)
2006#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
2007#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
2008#define CAN_MCR_RFLM_Pos (3U)
2009#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
2010#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
2011#define CAN_MCR_NART_Pos (4U)
2012#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
2013#define CAN_MCR_NART CAN_MCR_NART_Msk
2014#define CAN_MCR_AWUM_Pos (5U)
2015#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
2016#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
2017#define CAN_MCR_ABOM_Pos (6U)
2018#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
2019#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
2020#define CAN_MCR_TTCM_Pos (7U)
2021#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
2022#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
2023#define CAN_MCR_RESET_Pos (15U)
2024#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
2025#define CAN_MCR_RESET CAN_MCR_RESET_Msk
2026#define CAN_MCR_DBF_Pos (16U)
2027#define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos)
2028#define CAN_MCR_DBF CAN_MCR_DBF_Msk
2029/******************* Bit definition for CAN_MSR register ********************/
2030#define CAN_MSR_INAK_Pos (0U)
2031#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
2032#define CAN_MSR_INAK CAN_MSR_INAK_Msk
2033#define CAN_MSR_SLAK_Pos (1U)
2034#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
2035#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
2036#define CAN_MSR_ERRI_Pos (2U)
2037#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
2038#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
2039#define CAN_MSR_WKUI_Pos (3U)
2040#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
2041#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
2042#define CAN_MSR_SLAKI_Pos (4U)
2043#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
2044#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
2045#define CAN_MSR_TXM_Pos (8U)
2046#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
2047#define CAN_MSR_TXM CAN_MSR_TXM_Msk
2048#define CAN_MSR_RXM_Pos (9U)
2049#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
2050#define CAN_MSR_RXM CAN_MSR_RXM_Msk
2051#define CAN_MSR_SAMP_Pos (10U)
2052#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
2053#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
2054#define CAN_MSR_RX_Pos (11U)
2055#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
2056#define CAN_MSR_RX CAN_MSR_RX_Msk
2057
2058/******************* Bit definition for CAN_TSR register ********************/
2059#define CAN_TSR_RQCP0_Pos (0U)
2060#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
2061#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
2062#define CAN_TSR_TXOK0_Pos (1U)
2063#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
2064#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
2065#define CAN_TSR_ALST0_Pos (2U)
2066#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
2067#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
2068#define CAN_TSR_TERR0_Pos (3U)
2069#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
2070#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
2071#define CAN_TSR_ABRQ0_Pos (7U)
2072#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
2073#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
2074#define CAN_TSR_RQCP1_Pos (8U)
2075#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
2076#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
2077#define CAN_TSR_TXOK1_Pos (9U)
2078#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
2079#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
2080#define CAN_TSR_ALST1_Pos (10U)
2081#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
2082#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
2083#define CAN_TSR_TERR1_Pos (11U)
2084#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
2085#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
2086#define CAN_TSR_ABRQ1_Pos (15U)
2087#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
2088#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
2089#define CAN_TSR_RQCP2_Pos (16U)
2090#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
2091#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
2092#define CAN_TSR_TXOK2_Pos (17U)
2093#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
2094#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
2095#define CAN_TSR_ALST2_Pos (18U)
2096#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
2097#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
2098#define CAN_TSR_TERR2_Pos (19U)
2099#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
2100#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
2101#define CAN_TSR_ABRQ2_Pos (23U)
2102#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
2103#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
2104#define CAN_TSR_CODE_Pos (24U)
2105#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
2106#define CAN_TSR_CODE CAN_TSR_CODE_Msk
2107
2108#define CAN_TSR_TME_Pos (26U)
2109#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
2110#define CAN_TSR_TME CAN_TSR_TME_Msk
2111#define CAN_TSR_TME0_Pos (26U)
2112#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
2113#define CAN_TSR_TME0 CAN_TSR_TME0_Msk
2114#define CAN_TSR_TME1_Pos (27U)
2115#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
2116#define CAN_TSR_TME1 CAN_TSR_TME1_Msk
2117#define CAN_TSR_TME2_Pos (28U)
2118#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
2119#define CAN_TSR_TME2 CAN_TSR_TME2_Msk
2120
2121#define CAN_TSR_LOW_Pos (29U)
2122#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
2123#define CAN_TSR_LOW CAN_TSR_LOW_Msk
2124#define CAN_TSR_LOW0_Pos (29U)
2125#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
2126#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
2127#define CAN_TSR_LOW1_Pos (30U)
2128#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
2129#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
2130#define CAN_TSR_LOW2_Pos (31U)
2131#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
2132#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
2133
2134/******************* Bit definition for CAN_RF0R register *******************/
2135#define CAN_RF0R_FMP0_Pos (0U)
2136#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
2137#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
2138#define CAN_RF0R_FULL0_Pos (3U)
2139#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
2140#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
2141#define CAN_RF0R_FOVR0_Pos (4U)
2142#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
2143#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
2144#define CAN_RF0R_RFOM0_Pos (5U)
2145#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
2146#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
2147
2148/******************* Bit definition for CAN_RF1R register *******************/
2149#define CAN_RF1R_FMP1_Pos (0U)
2150#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
2151#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
2152#define CAN_RF1R_FULL1_Pos (3U)
2153#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
2154#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
2155#define CAN_RF1R_FOVR1_Pos (4U)
2156#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
2157#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
2158#define CAN_RF1R_RFOM1_Pos (5U)
2159#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
2160#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
2161
2162/******************** Bit definition for CAN_IER register *******************/
2163#define CAN_IER_TMEIE_Pos (0U)
2164#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
2165#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
2166#define CAN_IER_FMPIE0_Pos (1U)
2167#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
2168#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
2169#define CAN_IER_FFIE0_Pos (2U)
2170#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
2171#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
2172#define CAN_IER_FOVIE0_Pos (3U)
2173#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
2174#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
2175#define CAN_IER_FMPIE1_Pos (4U)
2176#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
2177#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
2178#define CAN_IER_FFIE1_Pos (5U)
2179#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
2180#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
2181#define CAN_IER_FOVIE1_Pos (6U)
2182#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
2183#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
2184#define CAN_IER_EWGIE_Pos (8U)
2185#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
2186#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
2187#define CAN_IER_EPVIE_Pos (9U)
2188#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
2189#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
2190#define CAN_IER_BOFIE_Pos (10U)
2191#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
2192#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
2193#define CAN_IER_LECIE_Pos (11U)
2194#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
2195#define CAN_IER_LECIE CAN_IER_LECIE_Msk
2196#define CAN_IER_ERRIE_Pos (15U)
2197#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
2198#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
2199#define CAN_IER_WKUIE_Pos (16U)
2200#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
2201#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
2202#define CAN_IER_SLKIE_Pos (17U)
2203#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
2204#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
2205#define CAN_IER_EWGIE_Pos (8U)
2206
2207/******************** Bit definition for CAN_ESR register *******************/
2208#define CAN_ESR_EWGF_Pos (0U)
2209#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
2210#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
2211#define CAN_ESR_EPVF_Pos (1U)
2212#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
2213#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
2214#define CAN_ESR_BOFF_Pos (2U)
2215#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
2216#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
2217
2218#define CAN_ESR_LEC_Pos (4U)
2219#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
2220#define CAN_ESR_LEC CAN_ESR_LEC_Msk
2221#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
2222#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
2223#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
2224
2225#define CAN_ESR_TEC_Pos (16U)
2226#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
2227#define CAN_ESR_TEC CAN_ESR_TEC_Msk
2228#define CAN_ESR_REC_Pos (24U)
2229#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
2230#define CAN_ESR_REC CAN_ESR_REC_Msk
2231
2232/******************* Bit definition for CAN_BTR register ********************/
2233#define CAN_BTR_BRP_Pos (0U)
2234#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
2235#define CAN_BTR_BRP CAN_BTR_BRP_Msk
2236#define CAN_BTR_TS1_Pos (16U)
2237#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
2238#define CAN_BTR_TS1 CAN_BTR_TS1_Msk
2239#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
2240#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
2241#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
2242#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
2243#define CAN_BTR_TS2_Pos (20U)
2244#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
2245#define CAN_BTR_TS2 CAN_BTR_TS2_Msk
2246#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
2247#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
2248#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
2249#define CAN_BTR_SJW_Pos (24U)
2250#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
2251#define CAN_BTR_SJW CAN_BTR_SJW_Msk
2252#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
2253#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
2254#define CAN_BTR_LBKM_Pos (30U)
2255#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
2256#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
2257#define CAN_BTR_SILM_Pos (31U)
2258#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
2259#define CAN_BTR_SILM CAN_BTR_SILM_Msk
2260
2261
2263/****************** Bit definition for CAN_TI0R register ********************/
2264#define CAN_TI0R_TXRQ_Pos (0U)
2265#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
2266#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
2267#define CAN_TI0R_RTR_Pos (1U)
2268#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
2269#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
2270#define CAN_TI0R_IDE_Pos (2U)
2271#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
2272#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
2273#define CAN_TI0R_EXID_Pos (3U)
2274#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
2275#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
2276#define CAN_TI0R_STID_Pos (21U)
2277#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
2278#define CAN_TI0R_STID CAN_TI0R_STID_Msk
2279
2280/****************** Bit definition for CAN_TDT0R register *******************/
2281#define CAN_TDT0R_DLC_Pos (0U)
2282#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
2283#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
2284#define CAN_TDT0R_TGT_Pos (8U)
2285#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
2286#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
2287#define CAN_TDT0R_TIME_Pos (16U)
2288#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
2289#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
2290
2291/****************** Bit definition for CAN_TDL0R register *******************/
2292#define CAN_TDL0R_DATA0_Pos (0U)
2293#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
2294#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
2295#define CAN_TDL0R_DATA1_Pos (8U)
2296#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
2297#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
2298#define CAN_TDL0R_DATA2_Pos (16U)
2299#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
2300#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
2301#define CAN_TDL0R_DATA3_Pos (24U)
2302#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
2303#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
2304
2305/****************** Bit definition for CAN_TDH0R register *******************/
2306#define CAN_TDH0R_DATA4_Pos (0U)
2307#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
2308#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
2309#define CAN_TDH0R_DATA5_Pos (8U)
2310#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
2311#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
2312#define CAN_TDH0R_DATA6_Pos (16U)
2313#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
2314#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
2315#define CAN_TDH0R_DATA7_Pos (24U)
2316#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
2317#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
2318
2319/******************* Bit definition for CAN_TI1R register *******************/
2320#define CAN_TI1R_TXRQ_Pos (0U)
2321#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
2322#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
2323#define CAN_TI1R_RTR_Pos (1U)
2324#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
2325#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
2326#define CAN_TI1R_IDE_Pos (2U)
2327#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
2328#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
2329#define CAN_TI1R_EXID_Pos (3U)
2330#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
2331#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
2332#define CAN_TI1R_STID_Pos (21U)
2333#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
2334#define CAN_TI1R_STID CAN_TI1R_STID_Msk
2335
2336/******************* Bit definition for CAN_TDT1R register ******************/
2337#define CAN_TDT1R_DLC_Pos (0U)
2338#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
2339#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
2340#define CAN_TDT1R_TGT_Pos (8U)
2341#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
2342#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
2343#define CAN_TDT1R_TIME_Pos (16U)
2344#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
2345#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
2346
2347/******************* Bit definition for CAN_TDL1R register ******************/
2348#define CAN_TDL1R_DATA0_Pos (0U)
2349#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
2350#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
2351#define CAN_TDL1R_DATA1_Pos (8U)
2352#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
2353#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
2354#define CAN_TDL1R_DATA2_Pos (16U)
2355#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
2356#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
2357#define CAN_TDL1R_DATA3_Pos (24U)
2358#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
2359#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
2360
2361/******************* Bit definition for CAN_TDH1R register ******************/
2362#define CAN_TDH1R_DATA4_Pos (0U)
2363#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
2364#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
2365#define CAN_TDH1R_DATA5_Pos (8U)
2366#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
2367#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
2368#define CAN_TDH1R_DATA6_Pos (16U)
2369#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
2370#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
2371#define CAN_TDH1R_DATA7_Pos (24U)
2372#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
2373#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
2374
2375/******************* Bit definition for CAN_TI2R register *******************/
2376#define CAN_TI2R_TXRQ_Pos (0U)
2377#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
2378#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
2379#define CAN_TI2R_RTR_Pos (1U)
2380#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
2381#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
2382#define CAN_TI2R_IDE_Pos (2U)
2383#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
2384#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
2385#define CAN_TI2R_EXID_Pos (3U)
2386#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
2387#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
2388#define CAN_TI2R_STID_Pos (21U)
2389#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
2390#define CAN_TI2R_STID CAN_TI2R_STID_Msk
2391
2392/******************* Bit definition for CAN_TDT2R register ******************/
2393#define CAN_TDT2R_DLC_Pos (0U)
2394#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
2395#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
2396#define CAN_TDT2R_TGT_Pos (8U)
2397#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
2398#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
2399#define CAN_TDT2R_TIME_Pos (16U)
2400#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
2401#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
2402
2403/******************* Bit definition for CAN_TDL2R register ******************/
2404#define CAN_TDL2R_DATA0_Pos (0U)
2405#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
2406#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
2407#define CAN_TDL2R_DATA1_Pos (8U)
2408#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
2409#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
2410#define CAN_TDL2R_DATA2_Pos (16U)
2411#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
2412#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
2413#define CAN_TDL2R_DATA3_Pos (24U)
2414#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
2415#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
2416
2417/******************* Bit definition for CAN_TDH2R register ******************/
2418#define CAN_TDH2R_DATA4_Pos (0U)
2419#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
2420#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
2421#define CAN_TDH2R_DATA5_Pos (8U)
2422#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
2423#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
2424#define CAN_TDH2R_DATA6_Pos (16U)
2425#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
2426#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
2427#define CAN_TDH2R_DATA7_Pos (24U)
2428#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
2429#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
2430
2431/******************* Bit definition for CAN_RI0R register *******************/
2432#define CAN_RI0R_RTR_Pos (1U)
2433#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
2434#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
2435#define CAN_RI0R_IDE_Pos (2U)
2436#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
2437#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
2438#define CAN_RI0R_EXID_Pos (3U)
2439#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
2440#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
2441#define CAN_RI0R_STID_Pos (21U)
2442#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
2443#define CAN_RI0R_STID CAN_RI0R_STID_Msk
2444
2445/******************* Bit definition for CAN_RDT0R register ******************/
2446#define CAN_RDT0R_DLC_Pos (0U)
2447#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
2448#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
2449#define CAN_RDT0R_FMI_Pos (8U)
2450#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
2451#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
2452#define CAN_RDT0R_TIME_Pos (16U)
2453#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
2454#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
2455
2456/******************* Bit definition for CAN_RDL0R register ******************/
2457#define CAN_RDL0R_DATA0_Pos (0U)
2458#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
2459#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
2460#define CAN_RDL0R_DATA1_Pos (8U)
2461#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
2462#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
2463#define CAN_RDL0R_DATA2_Pos (16U)
2464#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
2465#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
2466#define CAN_RDL0R_DATA3_Pos (24U)
2467#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
2468#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
2469
2470/******************* Bit definition for CAN_RDH0R register ******************/
2471#define CAN_RDH0R_DATA4_Pos (0U)
2472#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
2473#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
2474#define CAN_RDH0R_DATA5_Pos (8U)
2475#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
2476#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
2477#define CAN_RDH0R_DATA6_Pos (16U)
2478#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
2479#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
2480#define CAN_RDH0R_DATA7_Pos (24U)
2481#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
2482#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
2483
2484/******************* Bit definition for CAN_RI1R register *******************/
2485#define CAN_RI1R_RTR_Pos (1U)
2486#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
2487#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
2488#define CAN_RI1R_IDE_Pos (2U)
2489#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
2490#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
2491#define CAN_RI1R_EXID_Pos (3U)
2492#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
2493#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
2494#define CAN_RI1R_STID_Pos (21U)
2495#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
2496#define CAN_RI1R_STID CAN_RI1R_STID_Msk
2497
2498/******************* Bit definition for CAN_RDT1R register ******************/
2499#define CAN_RDT1R_DLC_Pos (0U)
2500#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
2501#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
2502#define CAN_RDT1R_FMI_Pos (8U)
2503#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
2504#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
2505#define CAN_RDT1R_TIME_Pos (16U)
2506#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
2507#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
2508
2509/******************* Bit definition for CAN_RDL1R register ******************/
2510#define CAN_RDL1R_DATA0_Pos (0U)
2511#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
2512#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
2513#define CAN_RDL1R_DATA1_Pos (8U)
2514#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
2515#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
2516#define CAN_RDL1R_DATA2_Pos (16U)
2517#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
2518#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
2519#define CAN_RDL1R_DATA3_Pos (24U)
2520#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
2521#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
2522
2523/******************* Bit definition for CAN_RDH1R register ******************/
2524#define CAN_RDH1R_DATA4_Pos (0U)
2525#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
2526#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
2527#define CAN_RDH1R_DATA5_Pos (8U)
2528#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
2529#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
2530#define CAN_RDH1R_DATA6_Pos (16U)
2531#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
2532#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
2533#define CAN_RDH1R_DATA7_Pos (24U)
2534#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
2535#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
2536
2538/******************* Bit definition for CAN_FMR register ********************/
2539#define CAN_FMR_FINIT_Pos (0U)
2540#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
2541#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
2542#define CAN_FMR_CAN2SB_Pos (8U)
2543#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
2544#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
2545
2546/******************* Bit definition for CAN_FM1R register *******************/
2547#define CAN_FM1R_FBM_Pos (0U)
2548#define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)
2549#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
2550#define CAN_FM1R_FBM0_Pos (0U)
2551#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
2552#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
2553#define CAN_FM1R_FBM1_Pos (1U)
2554#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
2555#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
2556#define CAN_FM1R_FBM2_Pos (2U)
2557#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
2558#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
2559#define CAN_FM1R_FBM3_Pos (3U)
2560#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
2561#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
2562#define CAN_FM1R_FBM4_Pos (4U)
2563#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
2564#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
2565#define CAN_FM1R_FBM5_Pos (5U)
2566#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
2567#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
2568#define CAN_FM1R_FBM6_Pos (6U)
2569#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
2570#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
2571#define CAN_FM1R_FBM7_Pos (7U)
2572#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
2573#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
2574#define CAN_FM1R_FBM8_Pos (8U)
2575#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
2576#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
2577#define CAN_FM1R_FBM9_Pos (9U)
2578#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
2579#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
2580#define CAN_FM1R_FBM10_Pos (10U)
2581#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
2582#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
2583#define CAN_FM1R_FBM11_Pos (11U)
2584#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
2585#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
2586#define CAN_FM1R_FBM12_Pos (12U)
2587#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
2588#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
2589#define CAN_FM1R_FBM13_Pos (13U)
2590#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
2591#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
2592#define CAN_FM1R_FBM14_Pos (14U)
2593#define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos)
2594#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk
2595#define CAN_FM1R_FBM15_Pos (15U)
2596#define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos)
2597#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk
2598#define CAN_FM1R_FBM16_Pos (16U)
2599#define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos)
2600#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk
2601#define CAN_FM1R_FBM17_Pos (17U)
2602#define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos)
2603#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk
2604#define CAN_FM1R_FBM18_Pos (18U)
2605#define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos)
2606#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk
2607#define CAN_FM1R_FBM19_Pos (19U)
2608#define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos)
2609#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk
2610#define CAN_FM1R_FBM20_Pos (20U)
2611#define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos)
2612#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk
2613#define CAN_FM1R_FBM21_Pos (21U)
2614#define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos)
2615#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk
2616#define CAN_FM1R_FBM22_Pos (22U)
2617#define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos)
2618#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk
2619#define CAN_FM1R_FBM23_Pos (23U)
2620#define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos)
2621#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk
2622#define CAN_FM1R_FBM24_Pos (24U)
2623#define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos)
2624#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk
2625#define CAN_FM1R_FBM25_Pos (25U)
2626#define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos)
2627#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk
2628#define CAN_FM1R_FBM26_Pos (26U)
2629#define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos)
2630#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk
2631#define CAN_FM1R_FBM27_Pos (27U)
2632#define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos)
2633#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk
2634
2635/******************* Bit definition for CAN_FS1R register *******************/
2636#define CAN_FS1R_FSC_Pos (0U)
2637#define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)
2638#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
2639#define CAN_FS1R_FSC0_Pos (0U)
2640#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
2641#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
2642#define CAN_FS1R_FSC1_Pos (1U)
2643#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
2644#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
2645#define CAN_FS1R_FSC2_Pos (2U)
2646#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
2647#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
2648#define CAN_FS1R_FSC3_Pos (3U)
2649#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
2650#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
2651#define CAN_FS1R_FSC4_Pos (4U)
2652#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
2653#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
2654#define CAN_FS1R_FSC5_Pos (5U)
2655#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
2656#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
2657#define CAN_FS1R_FSC6_Pos (6U)
2658#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
2659#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
2660#define CAN_FS1R_FSC7_Pos (7U)
2661#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
2662#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
2663#define CAN_FS1R_FSC8_Pos (8U)
2664#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
2665#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
2666#define CAN_FS1R_FSC9_Pos (9U)
2667#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
2668#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
2669#define CAN_FS1R_FSC10_Pos (10U)
2670#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
2671#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
2672#define CAN_FS1R_FSC11_Pos (11U)
2673#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
2674#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
2675#define CAN_FS1R_FSC12_Pos (12U)
2676#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
2677#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
2678#define CAN_FS1R_FSC13_Pos (13U)
2679#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
2680#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
2681#define CAN_FS1R_FSC14_Pos (14U)
2682#define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos)
2683#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk
2684#define CAN_FS1R_FSC15_Pos (15U)
2685#define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos)
2686#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk
2687#define CAN_FS1R_FSC16_Pos (16U)
2688#define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos)
2689#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk
2690#define CAN_FS1R_FSC17_Pos (17U)
2691#define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos)
2692#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk
2693#define CAN_FS1R_FSC18_Pos (18U)
2694#define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos)
2695#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk
2696#define CAN_FS1R_FSC19_Pos (19U)
2697#define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos)
2698#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk
2699#define CAN_FS1R_FSC20_Pos (20U)
2700#define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos)
2701#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk
2702#define CAN_FS1R_FSC21_Pos (21U)
2703#define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos)
2704#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk
2705#define CAN_FS1R_FSC22_Pos (22U)
2706#define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos)
2707#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk
2708#define CAN_FS1R_FSC23_Pos (23U)
2709#define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos)
2710#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk
2711#define CAN_FS1R_FSC24_Pos (24U)
2712#define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos)
2713#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk
2714#define CAN_FS1R_FSC25_Pos (25U)
2715#define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos)
2716#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk
2717#define CAN_FS1R_FSC26_Pos (26U)
2718#define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos)
2719#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk
2720#define CAN_FS1R_FSC27_Pos (27U)
2721#define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos)
2722#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk
2723
2724/****************** Bit definition for CAN_FFA1R register *******************/
2725#define CAN_FFA1R_FFA_Pos (0U)
2726#define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)
2727#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
2728#define CAN_FFA1R_FFA0_Pos (0U)
2729#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
2730#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
2731#define CAN_FFA1R_FFA1_Pos (1U)
2732#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
2733#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
2734#define CAN_FFA1R_FFA2_Pos (2U)
2735#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
2736#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
2737#define CAN_FFA1R_FFA3_Pos (3U)
2738#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
2739#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
2740#define CAN_FFA1R_FFA4_Pos (4U)
2741#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
2742#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
2743#define CAN_FFA1R_FFA5_Pos (5U)
2744#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
2745#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
2746#define CAN_FFA1R_FFA6_Pos (6U)
2747#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
2748#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
2749#define CAN_FFA1R_FFA7_Pos (7U)
2750#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
2751#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
2752#define CAN_FFA1R_FFA8_Pos (8U)
2753#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
2754#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
2755#define CAN_FFA1R_FFA9_Pos (9U)
2756#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
2757#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
2758#define CAN_FFA1R_FFA10_Pos (10U)
2759#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
2760#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
2761#define CAN_FFA1R_FFA11_Pos (11U)
2762#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
2763#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
2764#define CAN_FFA1R_FFA12_Pos (12U)
2765#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
2766#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
2767#define CAN_FFA1R_FFA13_Pos (13U)
2768#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
2769#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
2770#define CAN_FFA1R_FFA14_Pos (14U)
2771#define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos)
2772#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk
2773#define CAN_FFA1R_FFA15_Pos (15U)
2774#define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos)
2775#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk
2776#define CAN_FFA1R_FFA16_Pos (16U)
2777#define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos)
2778#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk
2779#define CAN_FFA1R_FFA17_Pos (17U)
2780#define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos)
2781#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk
2782#define CAN_FFA1R_FFA18_Pos (18U)
2783#define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos)
2784#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk
2785#define CAN_FFA1R_FFA19_Pos (19U)
2786#define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos)
2787#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk
2788#define CAN_FFA1R_FFA20_Pos (20U)
2789#define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos)
2790#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk
2791#define CAN_FFA1R_FFA21_Pos (21U)
2792#define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos)
2793#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk
2794#define CAN_FFA1R_FFA22_Pos (22U)
2795#define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos)
2796#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk
2797#define CAN_FFA1R_FFA23_Pos (23U)
2798#define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos)
2799#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk
2800#define CAN_FFA1R_FFA24_Pos (24U)
2801#define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos)
2802#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk
2803#define CAN_FFA1R_FFA25_Pos (25U)
2804#define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos)
2805#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk
2806#define CAN_FFA1R_FFA26_Pos (26U)
2807#define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos)
2808#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk
2809#define CAN_FFA1R_FFA27_Pos (27U)
2810#define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos)
2811#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk
2812
2813/******************* Bit definition for CAN_FA1R register *******************/
2814#define CAN_FA1R_FACT_Pos (0U)
2815#define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)
2816#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
2817#define CAN_FA1R_FACT0_Pos (0U)
2818#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
2819#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
2820#define CAN_FA1R_FACT1_Pos (1U)
2821#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
2822#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
2823#define CAN_FA1R_FACT2_Pos (2U)
2824#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
2825#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
2826#define CAN_FA1R_FACT3_Pos (3U)
2827#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
2828#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
2829#define CAN_FA1R_FACT4_Pos (4U)
2830#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
2831#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
2832#define CAN_FA1R_FACT5_Pos (5U)
2833#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
2834#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
2835#define CAN_FA1R_FACT6_Pos (6U)
2836#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
2837#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
2838#define CAN_FA1R_FACT7_Pos (7U)
2839#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
2840#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
2841#define CAN_FA1R_FACT8_Pos (8U)
2842#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
2843#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
2844#define CAN_FA1R_FACT9_Pos (9U)
2845#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
2846#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
2847#define CAN_FA1R_FACT10_Pos (10U)
2848#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
2849#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
2850#define CAN_FA1R_FACT11_Pos (11U)
2851#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
2852#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
2853#define CAN_FA1R_FACT12_Pos (12U)
2854#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
2855#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
2856#define CAN_FA1R_FACT13_Pos (13U)
2857#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
2858#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
2859#define CAN_FA1R_FACT14_Pos (14U)
2860#define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos)
2861#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk
2862#define CAN_FA1R_FACT15_Pos (15U)
2863#define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos)
2864#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk
2865#define CAN_FA1R_FACT16_Pos (16U)
2866#define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos)
2867#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk
2868#define CAN_FA1R_FACT17_Pos (17U)
2869#define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos)
2870#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk
2871#define CAN_FA1R_FACT18_Pos (18U)
2872#define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos)
2873#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk
2874#define CAN_FA1R_FACT19_Pos (19U)
2875#define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos)
2876#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk
2877#define CAN_FA1R_FACT20_Pos (20U)
2878#define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos)
2879#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk
2880#define CAN_FA1R_FACT21_Pos (21U)
2881#define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos)
2882#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk
2883#define CAN_FA1R_FACT22_Pos (22U)
2884#define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos)
2885#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk
2886#define CAN_FA1R_FACT23_Pos (23U)
2887#define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos)
2888#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk
2889#define CAN_FA1R_FACT24_Pos (24U)
2890#define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos)
2891#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk
2892#define CAN_FA1R_FACT25_Pos (25U)
2893#define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos)
2894#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk
2895#define CAN_FA1R_FACT26_Pos (26U)
2896#define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos)
2897#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk
2898#define CAN_FA1R_FACT27_Pos (27U)
2899#define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos)
2900#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk
2901
2902
2903/******************* Bit definition for CAN_F0R1 register *******************/
2904#define CAN_F0R1_FB0_Pos (0U)
2905#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
2906#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
2907#define CAN_F0R1_FB1_Pos (1U)
2908#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
2909#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
2910#define CAN_F0R1_FB2_Pos (2U)
2911#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
2912#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
2913#define CAN_F0R1_FB3_Pos (3U)
2914#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
2915#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
2916#define CAN_F0R1_FB4_Pos (4U)
2917#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
2918#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
2919#define CAN_F0R1_FB5_Pos (5U)
2920#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
2921#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
2922#define CAN_F0R1_FB6_Pos (6U)
2923#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
2924#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
2925#define CAN_F0R1_FB7_Pos (7U)
2926#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
2927#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
2928#define CAN_F0R1_FB8_Pos (8U)
2929#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
2930#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
2931#define CAN_F0R1_FB9_Pos (9U)
2932#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
2933#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
2934#define CAN_F0R1_FB10_Pos (10U)
2935#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
2936#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
2937#define CAN_F0R1_FB11_Pos (11U)
2938#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
2939#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
2940#define CAN_F0R1_FB12_Pos (12U)
2941#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
2942#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
2943#define CAN_F0R1_FB13_Pos (13U)
2944#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
2945#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
2946#define CAN_F0R1_FB14_Pos (14U)
2947#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
2948#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
2949#define CAN_F0R1_FB15_Pos (15U)
2950#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
2951#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
2952#define CAN_F0R1_FB16_Pos (16U)
2953#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
2954#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
2955#define CAN_F0R1_FB17_Pos (17U)
2956#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
2957#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
2958#define CAN_F0R1_FB18_Pos (18U)
2959#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
2960#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
2961#define CAN_F0R1_FB19_Pos (19U)
2962#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
2963#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
2964#define CAN_F0R1_FB20_Pos (20U)
2965#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
2966#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
2967#define CAN_F0R1_FB21_Pos (21U)
2968#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
2969#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
2970#define CAN_F0R1_FB22_Pos (22U)
2971#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
2972#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
2973#define CAN_F0R1_FB23_Pos (23U)
2974#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
2975#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
2976#define CAN_F0R1_FB24_Pos (24U)
2977#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
2978#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
2979#define CAN_F0R1_FB25_Pos (25U)
2980#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
2981#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
2982#define CAN_F0R1_FB26_Pos (26U)
2983#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
2984#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
2985#define CAN_F0R1_FB27_Pos (27U)
2986#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
2987#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
2988#define CAN_F0R1_FB28_Pos (28U)
2989#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
2990#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
2991#define CAN_F0R1_FB29_Pos (29U)
2992#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
2993#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
2994#define CAN_F0R1_FB30_Pos (30U)
2995#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
2996#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
2997#define CAN_F0R1_FB31_Pos (31U)
2998#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
2999#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
3000
3001/******************* Bit definition for CAN_F1R1 register *******************/
3002#define CAN_F1R1_FB0_Pos (0U)
3003#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
3004#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
3005#define CAN_F1R1_FB1_Pos (1U)
3006#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
3007#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
3008#define CAN_F1R1_FB2_Pos (2U)
3009#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
3010#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
3011#define CAN_F1R1_FB3_Pos (3U)
3012#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
3013#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
3014#define CAN_F1R1_FB4_Pos (4U)
3015#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
3016#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
3017#define CAN_F1R1_FB5_Pos (5U)
3018#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
3019#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
3020#define CAN_F1R1_FB6_Pos (6U)
3021#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
3022#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
3023#define CAN_F1R1_FB7_Pos (7U)
3024#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
3025#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
3026#define CAN_F1R1_FB8_Pos (8U)
3027#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
3028#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
3029#define CAN_F1R1_FB9_Pos (9U)
3030#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
3031#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
3032#define CAN_F1R1_FB10_Pos (10U)
3033#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
3034#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
3035#define CAN_F1R1_FB11_Pos (11U)
3036#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
3037#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
3038#define CAN_F1R1_FB12_Pos (12U)
3039#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
3040#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
3041#define CAN_F1R1_FB13_Pos (13U)
3042#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
3043#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
3044#define CAN_F1R1_FB14_Pos (14U)
3045#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
3046#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
3047#define CAN_F1R1_FB15_Pos (15U)
3048#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
3049#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
3050#define CAN_F1R1_FB16_Pos (16U)
3051#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
3052#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
3053#define CAN_F1R1_FB17_Pos (17U)
3054#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
3055#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
3056#define CAN_F1R1_FB18_Pos (18U)
3057#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
3058#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
3059#define CAN_F1R1_FB19_Pos (19U)
3060#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
3061#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
3062#define CAN_F1R1_FB20_Pos (20U)
3063#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
3064#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
3065#define CAN_F1R1_FB21_Pos (21U)
3066#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
3067#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
3068#define CAN_F1R1_FB22_Pos (22U)
3069#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
3070#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
3071#define CAN_F1R1_FB23_Pos (23U)
3072#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
3073#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
3074#define CAN_F1R1_FB24_Pos (24U)
3075#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
3076#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
3077#define CAN_F1R1_FB25_Pos (25U)
3078#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
3079#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
3080#define CAN_F1R1_FB26_Pos (26U)
3081#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
3082#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
3083#define CAN_F1R1_FB27_Pos (27U)
3084#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
3085#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
3086#define CAN_F1R1_FB28_Pos (28U)
3087#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
3088#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
3089#define CAN_F1R1_FB29_Pos (29U)
3090#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
3091#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
3092#define CAN_F1R1_FB30_Pos (30U)
3093#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
3094#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
3095#define CAN_F1R1_FB31_Pos (31U)
3096#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
3097#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
3098
3099/******************* Bit definition for CAN_F2R1 register *******************/
3100#define CAN_F2R1_FB0_Pos (0U)
3101#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
3102#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
3103#define CAN_F2R1_FB1_Pos (1U)
3104#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
3105#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
3106#define CAN_F2R1_FB2_Pos (2U)
3107#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
3108#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
3109#define CAN_F2R1_FB3_Pos (3U)
3110#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
3111#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
3112#define CAN_F2R1_FB4_Pos (4U)
3113#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
3114#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
3115#define CAN_F2R1_FB5_Pos (5U)
3116#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
3117#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
3118#define CAN_F2R1_FB6_Pos (6U)
3119#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
3120#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
3121#define CAN_F2R1_FB7_Pos (7U)
3122#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
3123#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
3124#define CAN_F2R1_FB8_Pos (8U)
3125#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
3126#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
3127#define CAN_F2R1_FB9_Pos (9U)
3128#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
3129#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
3130#define CAN_F2R1_FB10_Pos (10U)
3131#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
3132#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
3133#define CAN_F2R1_FB11_Pos (11U)
3134#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
3135#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
3136#define CAN_F2R1_FB12_Pos (12U)
3137#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
3138#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
3139#define CAN_F2R1_FB13_Pos (13U)
3140#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
3141#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
3142#define CAN_F2R1_FB14_Pos (14U)
3143#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
3144#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
3145#define CAN_F2R1_FB15_Pos (15U)
3146#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
3147#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
3148#define CAN_F2R1_FB16_Pos (16U)
3149#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
3150#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
3151#define CAN_F2R1_FB17_Pos (17U)
3152#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
3153#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
3154#define CAN_F2R1_FB18_Pos (18U)
3155#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
3156#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
3157#define CAN_F2R1_FB19_Pos (19U)
3158#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
3159#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
3160#define CAN_F2R1_FB20_Pos (20U)
3161#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
3162#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
3163#define CAN_F2R1_FB21_Pos (21U)
3164#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
3165#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
3166#define CAN_F2R1_FB22_Pos (22U)
3167#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
3168#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
3169#define CAN_F2R1_FB23_Pos (23U)
3170#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
3171#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
3172#define CAN_F2R1_FB24_Pos (24U)
3173#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
3174#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
3175#define CAN_F2R1_FB25_Pos (25U)
3176#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
3177#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
3178#define CAN_F2R1_FB26_Pos (26U)
3179#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
3180#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
3181#define CAN_F2R1_FB27_Pos (27U)
3182#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
3183#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
3184#define CAN_F2R1_FB28_Pos (28U)
3185#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
3186#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
3187#define CAN_F2R1_FB29_Pos (29U)
3188#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
3189#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
3190#define CAN_F2R1_FB30_Pos (30U)
3191#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
3192#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
3193#define CAN_F2R1_FB31_Pos (31U)
3194#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
3195#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
3196
3197/******************* Bit definition for CAN_F3R1 register *******************/
3198#define CAN_F3R1_FB0_Pos (0U)
3199#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
3200#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
3201#define CAN_F3R1_FB1_Pos (1U)
3202#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
3203#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
3204#define CAN_F3R1_FB2_Pos (2U)
3205#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
3206#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
3207#define CAN_F3R1_FB3_Pos (3U)
3208#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
3209#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
3210#define CAN_F3R1_FB4_Pos (4U)
3211#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
3212#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
3213#define CAN_F3R1_FB5_Pos (5U)
3214#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
3215#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
3216#define CAN_F3R1_FB6_Pos (6U)
3217#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
3218#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
3219#define CAN_F3R1_FB7_Pos (7U)
3220#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
3221#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
3222#define CAN_F3R1_FB8_Pos (8U)
3223#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
3224#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
3225#define CAN_F3R1_FB9_Pos (9U)
3226#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
3227#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
3228#define CAN_F3R1_FB10_Pos (10U)
3229#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
3230#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
3231#define CAN_F3R1_FB11_Pos (11U)
3232#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
3233#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
3234#define CAN_F3R1_FB12_Pos (12U)
3235#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
3236#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
3237#define CAN_F3R1_FB13_Pos (13U)
3238#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
3239#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
3240#define CAN_F3R1_FB14_Pos (14U)
3241#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
3242#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
3243#define CAN_F3R1_FB15_Pos (15U)
3244#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
3245#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
3246#define CAN_F3R1_FB16_Pos (16U)
3247#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
3248#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
3249#define CAN_F3R1_FB17_Pos (17U)
3250#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
3251#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
3252#define CAN_F3R1_FB18_Pos (18U)
3253#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
3254#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
3255#define CAN_F3R1_FB19_Pos (19U)
3256#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
3257#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
3258#define CAN_F3R1_FB20_Pos (20U)
3259#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
3260#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
3261#define CAN_F3R1_FB21_Pos (21U)
3262#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
3263#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
3264#define CAN_F3R1_FB22_Pos (22U)
3265#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
3266#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
3267#define CAN_F3R1_FB23_Pos (23U)
3268#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
3269#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
3270#define CAN_F3R1_FB24_Pos (24U)
3271#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
3272#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
3273#define CAN_F3R1_FB25_Pos (25U)
3274#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
3275#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
3276#define CAN_F3R1_FB26_Pos (26U)
3277#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
3278#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
3279#define CAN_F3R1_FB27_Pos (27U)
3280#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
3281#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
3282#define CAN_F3R1_FB28_Pos (28U)
3283#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
3284#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
3285#define CAN_F3R1_FB29_Pos (29U)
3286#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
3287#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
3288#define CAN_F3R1_FB30_Pos (30U)
3289#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
3290#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
3291#define CAN_F3R1_FB31_Pos (31U)
3292#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
3293#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
3294
3295/******************* Bit definition for CAN_F4R1 register *******************/
3296#define CAN_F4R1_FB0_Pos (0U)
3297#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
3298#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
3299#define CAN_F4R1_FB1_Pos (1U)
3300#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
3301#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
3302#define CAN_F4R1_FB2_Pos (2U)
3303#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
3304#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
3305#define CAN_F4R1_FB3_Pos (3U)
3306#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
3307#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
3308#define CAN_F4R1_FB4_Pos (4U)
3309#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
3310#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
3311#define CAN_F4R1_FB5_Pos (5U)
3312#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
3313#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
3314#define CAN_F4R1_FB6_Pos (6U)
3315#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
3316#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
3317#define CAN_F4R1_FB7_Pos (7U)
3318#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
3319#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
3320#define CAN_F4R1_FB8_Pos (8U)
3321#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
3322#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
3323#define CAN_F4R1_FB9_Pos (9U)
3324#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
3325#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
3326#define CAN_F4R1_FB10_Pos (10U)
3327#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
3328#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
3329#define CAN_F4R1_FB11_Pos (11U)
3330#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
3331#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
3332#define CAN_F4R1_FB12_Pos (12U)
3333#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
3334#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
3335#define CAN_F4R1_FB13_Pos (13U)
3336#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
3337#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
3338#define CAN_F4R1_FB14_Pos (14U)
3339#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
3340#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
3341#define CAN_F4R1_FB15_Pos (15U)
3342#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
3343#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
3344#define CAN_F4R1_FB16_Pos (16U)
3345#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
3346#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
3347#define CAN_F4R1_FB17_Pos (17U)
3348#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
3349#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
3350#define CAN_F4R1_FB18_Pos (18U)
3351#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
3352#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
3353#define CAN_F4R1_FB19_Pos (19U)
3354#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
3355#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
3356#define CAN_F4R1_FB20_Pos (20U)
3357#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
3358#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
3359#define CAN_F4R1_FB21_Pos (21U)
3360#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
3361#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
3362#define CAN_F4R1_FB22_Pos (22U)
3363#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
3364#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
3365#define CAN_F4R1_FB23_Pos (23U)
3366#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
3367#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
3368#define CAN_F4R1_FB24_Pos (24U)
3369#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
3370#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
3371#define CAN_F4R1_FB25_Pos (25U)
3372#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
3373#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
3374#define CAN_F4R1_FB26_Pos (26U)
3375#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
3376#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
3377#define CAN_F4R1_FB27_Pos (27U)
3378#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
3379#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
3380#define CAN_F4R1_FB28_Pos (28U)
3381#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
3382#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
3383#define CAN_F4R1_FB29_Pos (29U)
3384#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
3385#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
3386#define CAN_F4R1_FB30_Pos (30U)
3387#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
3388#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
3389#define CAN_F4R1_FB31_Pos (31U)
3390#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
3391#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
3392
3393/******************* Bit definition for CAN_F5R1 register *******************/
3394#define CAN_F5R1_FB0_Pos (0U)
3395#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
3396#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
3397#define CAN_F5R1_FB1_Pos (1U)
3398#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
3399#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
3400#define CAN_F5R1_FB2_Pos (2U)
3401#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
3402#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
3403#define CAN_F5R1_FB3_Pos (3U)
3404#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
3405#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
3406#define CAN_F5R1_FB4_Pos (4U)
3407#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
3408#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
3409#define CAN_F5R1_FB5_Pos (5U)
3410#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
3411#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
3412#define CAN_F5R1_FB6_Pos (6U)
3413#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
3414#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
3415#define CAN_F5R1_FB7_Pos (7U)
3416#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
3417#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
3418#define CAN_F5R1_FB8_Pos (8U)
3419#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
3420#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
3421#define CAN_F5R1_FB9_Pos (9U)
3422#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
3423#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
3424#define CAN_F5R1_FB10_Pos (10U)
3425#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
3426#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
3427#define CAN_F5R1_FB11_Pos (11U)
3428#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
3429#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
3430#define CAN_F5R1_FB12_Pos (12U)
3431#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
3432#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
3433#define CAN_F5R1_FB13_Pos (13U)
3434#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
3435#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
3436#define CAN_F5R1_FB14_Pos (14U)
3437#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
3438#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
3439#define CAN_F5R1_FB15_Pos (15U)
3440#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
3441#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
3442#define CAN_F5R1_FB16_Pos (16U)
3443#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
3444#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
3445#define CAN_F5R1_FB17_Pos (17U)
3446#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
3447#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
3448#define CAN_F5R1_FB18_Pos (18U)
3449#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
3450#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
3451#define CAN_F5R1_FB19_Pos (19U)
3452#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
3453#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
3454#define CAN_F5R1_FB20_Pos (20U)
3455#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
3456#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
3457#define CAN_F5R1_FB21_Pos (21U)
3458#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
3459#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
3460#define CAN_F5R1_FB22_Pos (22U)
3461#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
3462#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
3463#define CAN_F5R1_FB23_Pos (23U)
3464#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
3465#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
3466#define CAN_F5R1_FB24_Pos (24U)
3467#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
3468#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
3469#define CAN_F5R1_FB25_Pos (25U)
3470#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
3471#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
3472#define CAN_F5R1_FB26_Pos (26U)
3473#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
3474#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
3475#define CAN_F5R1_FB27_Pos (27U)
3476#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
3477#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
3478#define CAN_F5R1_FB28_Pos (28U)
3479#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
3480#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
3481#define CAN_F5R1_FB29_Pos (29U)
3482#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
3483#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
3484#define CAN_F5R1_FB30_Pos (30U)
3485#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
3486#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
3487#define CAN_F5R1_FB31_Pos (31U)
3488#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
3489#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
3490
3491/******************* Bit definition for CAN_F6R1 register *******************/
3492#define CAN_F6R1_FB0_Pos (0U)
3493#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
3494#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
3495#define CAN_F6R1_FB1_Pos (1U)
3496#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
3497#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
3498#define CAN_F6R1_FB2_Pos (2U)
3499#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
3500#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
3501#define CAN_F6R1_FB3_Pos (3U)
3502#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
3503#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
3504#define CAN_F6R1_FB4_Pos (4U)
3505#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
3506#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
3507#define CAN_F6R1_FB5_Pos (5U)
3508#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
3509#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
3510#define CAN_F6R1_FB6_Pos (6U)
3511#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
3512#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
3513#define CAN_F6R1_FB7_Pos (7U)
3514#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
3515#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
3516#define CAN_F6R1_FB8_Pos (8U)
3517#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
3518#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
3519#define CAN_F6R1_FB9_Pos (9U)
3520#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
3521#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
3522#define CAN_F6R1_FB10_Pos (10U)
3523#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
3524#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
3525#define CAN_F6R1_FB11_Pos (11U)
3526#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
3527#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
3528#define CAN_F6R1_FB12_Pos (12U)
3529#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
3530#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
3531#define CAN_F6R1_FB13_Pos (13U)
3532#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
3533#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
3534#define CAN_F6R1_FB14_Pos (14U)
3535#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
3536#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
3537#define CAN_F6R1_FB15_Pos (15U)
3538#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
3539#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
3540#define CAN_F6R1_FB16_Pos (16U)
3541#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
3542#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
3543#define CAN_F6R1_FB17_Pos (17U)
3544#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
3545#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
3546#define CAN_F6R1_FB18_Pos (18U)
3547#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
3548#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
3549#define CAN_F6R1_FB19_Pos (19U)
3550#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
3551#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
3552#define CAN_F6R1_FB20_Pos (20U)
3553#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
3554#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
3555#define CAN_F6R1_FB21_Pos (21U)
3556#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
3557#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
3558#define CAN_F6R1_FB22_Pos (22U)
3559#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
3560#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
3561#define CAN_F6R1_FB23_Pos (23U)
3562#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
3563#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
3564#define CAN_F6R1_FB24_Pos (24U)
3565#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
3566#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
3567#define CAN_F6R1_FB25_Pos (25U)
3568#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
3569#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
3570#define CAN_F6R1_FB26_Pos (26U)
3571#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
3572#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
3573#define CAN_F6R1_FB27_Pos (27U)
3574#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
3575#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
3576#define CAN_F6R1_FB28_Pos (28U)
3577#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
3578#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
3579#define CAN_F6R1_FB29_Pos (29U)
3580#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
3581#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
3582#define CAN_F6R1_FB30_Pos (30U)
3583#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
3584#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
3585#define CAN_F6R1_FB31_Pos (31U)
3586#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
3587#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
3588
3589/******************* Bit definition for CAN_F7R1 register *******************/
3590#define CAN_F7R1_FB0_Pos (0U)
3591#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
3592#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
3593#define CAN_F7R1_FB1_Pos (1U)
3594#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
3595#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
3596#define CAN_F7R1_FB2_Pos (2U)
3597#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
3598#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
3599#define CAN_F7R1_FB3_Pos (3U)
3600#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
3601#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
3602#define CAN_F7R1_FB4_Pos (4U)
3603#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
3604#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
3605#define CAN_F7R1_FB5_Pos (5U)
3606#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
3607#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
3608#define CAN_F7R1_FB6_Pos (6U)
3609#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
3610#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
3611#define CAN_F7R1_FB7_Pos (7U)
3612#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
3613#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
3614#define CAN_F7R1_FB8_Pos (8U)
3615#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
3616#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
3617#define CAN_F7R1_FB9_Pos (9U)
3618#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
3619#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
3620#define CAN_F7R1_FB10_Pos (10U)
3621#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
3622#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
3623#define CAN_F7R1_FB11_Pos (11U)
3624#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
3625#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
3626#define CAN_F7R1_FB12_Pos (12U)
3627#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
3628#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
3629#define CAN_F7R1_FB13_Pos (13U)
3630#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
3631#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
3632#define CAN_F7R1_FB14_Pos (14U)
3633#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
3634#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
3635#define CAN_F7R1_FB15_Pos (15U)
3636#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
3637#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
3638#define CAN_F7R1_FB16_Pos (16U)
3639#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
3640#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
3641#define CAN_F7R1_FB17_Pos (17U)
3642#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
3643#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
3644#define CAN_F7R1_FB18_Pos (18U)
3645#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
3646#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
3647#define CAN_F7R1_FB19_Pos (19U)
3648#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
3649#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
3650#define CAN_F7R1_FB20_Pos (20U)
3651#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
3652#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
3653#define CAN_F7R1_FB21_Pos (21U)
3654#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
3655#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
3656#define CAN_F7R1_FB22_Pos (22U)
3657#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
3658#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
3659#define CAN_F7R1_FB23_Pos (23U)
3660#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
3661#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
3662#define CAN_F7R1_FB24_Pos (24U)
3663#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
3664#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
3665#define CAN_F7R1_FB25_Pos (25U)
3666#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
3667#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
3668#define CAN_F7R1_FB26_Pos (26U)
3669#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
3670#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
3671#define CAN_F7R1_FB27_Pos (27U)
3672#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
3673#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
3674#define CAN_F7R1_FB28_Pos (28U)
3675#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
3676#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
3677#define CAN_F7R1_FB29_Pos (29U)
3678#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
3679#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
3680#define CAN_F7R1_FB30_Pos (30U)
3681#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
3682#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
3683#define CAN_F7R1_FB31_Pos (31U)
3684#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
3685#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
3686
3687/******************* Bit definition for CAN_F8R1 register *******************/
3688#define CAN_F8R1_FB0_Pos (0U)
3689#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
3690#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
3691#define CAN_F8R1_FB1_Pos (1U)
3692#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
3693#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
3694#define CAN_F8R1_FB2_Pos (2U)
3695#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
3696#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
3697#define CAN_F8R1_FB3_Pos (3U)
3698#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
3699#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
3700#define CAN_F8R1_FB4_Pos (4U)
3701#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
3702#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
3703#define CAN_F8R1_FB5_Pos (5U)
3704#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
3705#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
3706#define CAN_F8R1_FB6_Pos (6U)
3707#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
3708#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
3709#define CAN_F8R1_FB7_Pos (7U)
3710#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
3711#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
3712#define CAN_F8R1_FB8_Pos (8U)
3713#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
3714#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
3715#define CAN_F8R1_FB9_Pos (9U)
3716#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
3717#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
3718#define CAN_F8R1_FB10_Pos (10U)
3719#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
3720#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
3721#define CAN_F8R1_FB11_Pos (11U)
3722#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
3723#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
3724#define CAN_F8R1_FB12_Pos (12U)
3725#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
3726#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
3727#define CAN_F8R1_FB13_Pos (13U)
3728#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
3729#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
3730#define CAN_F8R1_FB14_Pos (14U)
3731#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
3732#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
3733#define CAN_F8R1_FB15_Pos (15U)
3734#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
3735#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
3736#define CAN_F8R1_FB16_Pos (16U)
3737#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
3738#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
3739#define CAN_F8R1_FB17_Pos (17U)
3740#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
3741#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
3742#define CAN_F8R1_FB18_Pos (18U)
3743#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
3744#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
3745#define CAN_F8R1_FB19_Pos (19U)
3746#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
3747#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
3748#define CAN_F8R1_FB20_Pos (20U)
3749#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
3750#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
3751#define CAN_F8R1_FB21_Pos (21U)
3752#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
3753#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
3754#define CAN_F8R1_FB22_Pos (22U)
3755#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
3756#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
3757#define CAN_F8R1_FB23_Pos (23U)
3758#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
3759#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
3760#define CAN_F8R1_FB24_Pos (24U)
3761#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
3762#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
3763#define CAN_F8R1_FB25_Pos (25U)
3764#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
3765#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
3766#define CAN_F8R1_FB26_Pos (26U)
3767#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
3768#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
3769#define CAN_F8R1_FB27_Pos (27U)
3770#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
3771#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
3772#define CAN_F8R1_FB28_Pos (28U)
3773#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
3774#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
3775#define CAN_F8R1_FB29_Pos (29U)
3776#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
3777#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
3778#define CAN_F8R1_FB30_Pos (30U)
3779#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
3780#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
3781#define CAN_F8R1_FB31_Pos (31U)
3782#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
3783#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
3784
3785/******************* Bit definition for CAN_F9R1 register *******************/
3786#define CAN_F9R1_FB0_Pos (0U)
3787#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
3788#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
3789#define CAN_F9R1_FB1_Pos (1U)
3790#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
3791#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
3792#define CAN_F9R1_FB2_Pos (2U)
3793#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
3794#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
3795#define CAN_F9R1_FB3_Pos (3U)
3796#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
3797#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
3798#define CAN_F9R1_FB4_Pos (4U)
3799#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
3800#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
3801#define CAN_F9R1_FB5_Pos (5U)
3802#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
3803#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
3804#define CAN_F9R1_FB6_Pos (6U)
3805#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
3806#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
3807#define CAN_F9R1_FB7_Pos (7U)
3808#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
3809#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
3810#define CAN_F9R1_FB8_Pos (8U)
3811#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
3812#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
3813#define CAN_F9R1_FB9_Pos (9U)
3814#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
3815#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
3816#define CAN_F9R1_FB10_Pos (10U)
3817#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
3818#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
3819#define CAN_F9R1_FB11_Pos (11U)
3820#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
3821#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
3822#define CAN_F9R1_FB12_Pos (12U)
3823#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
3824#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
3825#define CAN_F9R1_FB13_Pos (13U)
3826#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
3827#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
3828#define CAN_F9R1_FB14_Pos (14U)
3829#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
3830#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
3831#define CAN_F9R1_FB15_Pos (15U)
3832#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
3833#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
3834#define CAN_F9R1_FB16_Pos (16U)
3835#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
3836#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
3837#define CAN_F9R1_FB17_Pos (17U)
3838#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
3839#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
3840#define CAN_F9R1_FB18_Pos (18U)
3841#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
3842#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
3843#define CAN_F9R1_FB19_Pos (19U)
3844#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
3845#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
3846#define CAN_F9R1_FB20_Pos (20U)
3847#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
3848#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
3849#define CAN_F9R1_FB21_Pos (21U)
3850#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
3851#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
3852#define CAN_F9R1_FB22_Pos (22U)
3853#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
3854#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
3855#define CAN_F9R1_FB23_Pos (23U)
3856#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
3857#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
3858#define CAN_F9R1_FB24_Pos (24U)
3859#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
3860#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
3861#define CAN_F9R1_FB25_Pos (25U)
3862#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
3863#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
3864#define CAN_F9R1_FB26_Pos (26U)
3865#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
3866#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
3867#define CAN_F9R1_FB27_Pos (27U)
3868#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
3869#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
3870#define CAN_F9R1_FB28_Pos (28U)
3871#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
3872#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
3873#define CAN_F9R1_FB29_Pos (29U)
3874#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
3875#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
3876#define CAN_F9R1_FB30_Pos (30U)
3877#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
3878#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
3879#define CAN_F9R1_FB31_Pos (31U)
3880#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
3881#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
3882
3883/******************* Bit definition for CAN_F10R1 register ******************/
3884#define CAN_F10R1_FB0_Pos (0U)
3885#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
3886#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
3887#define CAN_F10R1_FB1_Pos (1U)
3888#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
3889#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
3890#define CAN_F10R1_FB2_Pos (2U)
3891#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
3892#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
3893#define CAN_F10R1_FB3_Pos (3U)
3894#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
3895#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
3896#define CAN_F10R1_FB4_Pos (4U)
3897#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
3898#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
3899#define CAN_F10R1_FB5_Pos (5U)
3900#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
3901#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
3902#define CAN_F10R1_FB6_Pos (6U)
3903#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
3904#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
3905#define CAN_F10R1_FB7_Pos (7U)
3906#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
3907#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
3908#define CAN_F10R1_FB8_Pos (8U)
3909#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
3910#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
3911#define CAN_F10R1_FB9_Pos (9U)
3912#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
3913#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
3914#define CAN_F10R1_FB10_Pos (10U)
3915#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
3916#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
3917#define CAN_F10R1_FB11_Pos (11U)
3918#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
3919#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
3920#define CAN_F10R1_FB12_Pos (12U)
3921#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
3922#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
3923#define CAN_F10R1_FB13_Pos (13U)
3924#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
3925#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
3926#define CAN_F10R1_FB14_Pos (14U)
3927#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
3928#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
3929#define CAN_F10R1_FB15_Pos (15U)
3930#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
3931#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
3932#define CAN_F10R1_FB16_Pos (16U)
3933#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
3934#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
3935#define CAN_F10R1_FB17_Pos (17U)
3936#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
3937#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
3938#define CAN_F10R1_FB18_Pos (18U)
3939#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
3940#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
3941#define CAN_F10R1_FB19_Pos (19U)
3942#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
3943#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
3944#define CAN_F10R1_FB20_Pos (20U)
3945#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
3946#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
3947#define CAN_F10R1_FB21_Pos (21U)
3948#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
3949#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
3950#define CAN_F10R1_FB22_Pos (22U)
3951#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
3952#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
3953#define CAN_F10R1_FB23_Pos (23U)
3954#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
3955#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
3956#define CAN_F10R1_FB24_Pos (24U)
3957#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
3958#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
3959#define CAN_F10R1_FB25_Pos (25U)
3960#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
3961#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
3962#define CAN_F10R1_FB26_Pos (26U)
3963#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
3964#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
3965#define CAN_F10R1_FB27_Pos (27U)
3966#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
3967#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
3968#define CAN_F10R1_FB28_Pos (28U)
3969#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
3970#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
3971#define CAN_F10R1_FB29_Pos (29U)
3972#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
3973#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
3974#define CAN_F10R1_FB30_Pos (30U)
3975#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
3976#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
3977#define CAN_F10R1_FB31_Pos (31U)
3978#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
3979#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
3980
3981/******************* Bit definition for CAN_F11R1 register ******************/
3982#define CAN_F11R1_FB0_Pos (0U)
3983#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
3984#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
3985#define CAN_F11R1_FB1_Pos (1U)
3986#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
3987#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
3988#define CAN_F11R1_FB2_Pos (2U)
3989#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
3990#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
3991#define CAN_F11R1_FB3_Pos (3U)
3992#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
3993#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
3994#define CAN_F11R1_FB4_Pos (4U)
3995#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
3996#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
3997#define CAN_F11R1_FB5_Pos (5U)
3998#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
3999#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
4000#define CAN_F11R1_FB6_Pos (6U)
4001#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
4002#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
4003#define CAN_F11R1_FB7_Pos (7U)
4004#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
4005#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
4006#define CAN_F11R1_FB8_Pos (8U)
4007#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
4008#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
4009#define CAN_F11R1_FB9_Pos (9U)
4010#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
4011#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
4012#define CAN_F11R1_FB10_Pos (10U)
4013#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
4014#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
4015#define CAN_F11R1_FB11_Pos (11U)
4016#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
4017#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
4018#define CAN_F11R1_FB12_Pos (12U)
4019#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
4020#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
4021#define CAN_F11R1_FB13_Pos (13U)
4022#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
4023#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
4024#define CAN_F11R1_FB14_Pos (14U)
4025#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
4026#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
4027#define CAN_F11R1_FB15_Pos (15U)
4028#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
4029#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
4030#define CAN_F11R1_FB16_Pos (16U)
4031#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
4032#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
4033#define CAN_F11R1_FB17_Pos (17U)
4034#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
4035#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
4036#define CAN_F11R1_FB18_Pos (18U)
4037#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
4038#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
4039#define CAN_F11R1_FB19_Pos (19U)
4040#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
4041#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
4042#define CAN_F11R1_FB20_Pos (20U)
4043#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
4044#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
4045#define CAN_F11R1_FB21_Pos (21U)
4046#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
4047#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
4048#define CAN_F11R1_FB22_Pos (22U)
4049#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
4050#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
4051#define CAN_F11R1_FB23_Pos (23U)
4052#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
4053#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
4054#define CAN_F11R1_FB24_Pos (24U)
4055#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
4056#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
4057#define CAN_F11R1_FB25_Pos (25U)
4058#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
4059#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
4060#define CAN_F11R1_FB26_Pos (26U)
4061#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
4062#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
4063#define CAN_F11R1_FB27_Pos (27U)
4064#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
4065#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
4066#define CAN_F11R1_FB28_Pos (28U)
4067#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
4068#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
4069#define CAN_F11R1_FB29_Pos (29U)
4070#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
4071#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
4072#define CAN_F11R1_FB30_Pos (30U)
4073#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
4074#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
4075#define CAN_F11R1_FB31_Pos (31U)
4076#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
4077#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
4078
4079/******************* Bit definition for CAN_F12R1 register ******************/
4080#define CAN_F12R1_FB0_Pos (0U)
4081#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
4082#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
4083#define CAN_F12R1_FB1_Pos (1U)
4084#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
4085#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
4086#define CAN_F12R1_FB2_Pos (2U)
4087#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
4088#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
4089#define CAN_F12R1_FB3_Pos (3U)
4090#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
4091#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
4092#define CAN_F12R1_FB4_Pos (4U)
4093#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
4094#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
4095#define CAN_F12R1_FB5_Pos (5U)
4096#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
4097#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
4098#define CAN_F12R1_FB6_Pos (6U)
4099#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
4100#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
4101#define CAN_F12R1_FB7_Pos (7U)
4102#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
4103#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
4104#define CAN_F12R1_FB8_Pos (8U)
4105#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
4106#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
4107#define CAN_F12R1_FB9_Pos (9U)
4108#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
4109#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
4110#define CAN_F12R1_FB10_Pos (10U)
4111#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
4112#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
4113#define CAN_F12R1_FB11_Pos (11U)
4114#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
4115#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
4116#define CAN_F12R1_FB12_Pos (12U)
4117#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
4118#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
4119#define CAN_F12R1_FB13_Pos (13U)
4120#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
4121#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
4122#define CAN_F12R1_FB14_Pos (14U)
4123#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
4124#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
4125#define CAN_F12R1_FB15_Pos (15U)
4126#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
4127#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
4128#define CAN_F12R1_FB16_Pos (16U)
4129#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
4130#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
4131#define CAN_F12R1_FB17_Pos (17U)
4132#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
4133#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
4134#define CAN_F12R1_FB18_Pos (18U)
4135#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
4136#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
4137#define CAN_F12R1_FB19_Pos (19U)
4138#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
4139#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
4140#define CAN_F12R1_FB20_Pos (20U)
4141#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
4142#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
4143#define CAN_F12R1_FB21_Pos (21U)
4144#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
4145#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
4146#define CAN_F12R1_FB22_Pos (22U)
4147#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
4148#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
4149#define CAN_F12R1_FB23_Pos (23U)
4150#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
4151#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
4152#define CAN_F12R1_FB24_Pos (24U)
4153#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
4154#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
4155#define CAN_F12R1_FB25_Pos (25U)
4156#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
4157#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
4158#define CAN_F12R1_FB26_Pos (26U)
4159#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
4160#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
4161#define CAN_F12R1_FB27_Pos (27U)
4162#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
4163#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
4164#define CAN_F12R1_FB28_Pos (28U)
4165#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
4166#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
4167#define CAN_F12R1_FB29_Pos (29U)
4168#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
4169#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
4170#define CAN_F12R1_FB30_Pos (30U)
4171#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
4172#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
4173#define CAN_F12R1_FB31_Pos (31U)
4174#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
4175#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
4176
4177/******************* Bit definition for CAN_F13R1 register ******************/
4178#define CAN_F13R1_FB0_Pos (0U)
4179#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
4180#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
4181#define CAN_F13R1_FB1_Pos (1U)
4182#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
4183#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
4184#define CAN_F13R1_FB2_Pos (2U)
4185#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
4186#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
4187#define CAN_F13R1_FB3_Pos (3U)
4188#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
4189#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
4190#define CAN_F13R1_FB4_Pos (4U)
4191#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
4192#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
4193#define CAN_F13R1_FB5_Pos (5U)
4194#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
4195#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
4196#define CAN_F13R1_FB6_Pos (6U)
4197#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
4198#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
4199#define CAN_F13R1_FB7_Pos (7U)
4200#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
4201#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
4202#define CAN_F13R1_FB8_Pos (8U)
4203#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
4204#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
4205#define CAN_F13R1_FB9_Pos (9U)
4206#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
4207#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
4208#define CAN_F13R1_FB10_Pos (10U)
4209#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
4210#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
4211#define CAN_F13R1_FB11_Pos (11U)
4212#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
4213#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
4214#define CAN_F13R1_FB12_Pos (12U)
4215#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
4216#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
4217#define CAN_F13R1_FB13_Pos (13U)
4218#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
4219#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
4220#define CAN_F13R1_FB14_Pos (14U)
4221#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
4222#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
4223#define CAN_F13R1_FB15_Pos (15U)
4224#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
4225#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
4226#define CAN_F13R1_FB16_Pos (16U)
4227#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
4228#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
4229#define CAN_F13R1_FB17_Pos (17U)
4230#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
4231#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
4232#define CAN_F13R1_FB18_Pos (18U)
4233#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
4234#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
4235#define CAN_F13R1_FB19_Pos (19U)
4236#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
4237#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
4238#define CAN_F13R1_FB20_Pos (20U)
4239#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
4240#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
4241#define CAN_F13R1_FB21_Pos (21U)
4242#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
4243#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
4244#define CAN_F13R1_FB22_Pos (22U)
4245#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
4246#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
4247#define CAN_F13R1_FB23_Pos (23U)
4248#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
4249#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
4250#define CAN_F13R1_FB24_Pos (24U)
4251#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
4252#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
4253#define CAN_F13R1_FB25_Pos (25U)
4254#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
4255#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
4256#define CAN_F13R1_FB26_Pos (26U)
4257#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
4258#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
4259#define CAN_F13R1_FB27_Pos (27U)
4260#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
4261#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
4262#define CAN_F13R1_FB28_Pos (28U)
4263#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
4264#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
4265#define CAN_F13R1_FB29_Pos (29U)
4266#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
4267#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
4268#define CAN_F13R1_FB30_Pos (30U)
4269#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
4270#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
4271#define CAN_F13R1_FB31_Pos (31U)
4272#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
4273#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
4274
4275/******************* Bit definition for CAN_F0R2 register *******************/
4276#define CAN_F0R2_FB0_Pos (0U)
4277#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
4278#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
4279#define CAN_F0R2_FB1_Pos (1U)
4280#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
4281#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
4282#define CAN_F0R2_FB2_Pos (2U)
4283#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
4284#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
4285#define CAN_F0R2_FB3_Pos (3U)
4286#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
4287#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
4288#define CAN_F0R2_FB4_Pos (4U)
4289#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
4290#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
4291#define CAN_F0R2_FB5_Pos (5U)
4292#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
4293#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
4294#define CAN_F0R2_FB6_Pos (6U)
4295#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
4296#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
4297#define CAN_F0R2_FB7_Pos (7U)
4298#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
4299#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
4300#define CAN_F0R2_FB8_Pos (8U)
4301#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
4302#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
4303#define CAN_F0R2_FB9_Pos (9U)
4304#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
4305#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
4306#define CAN_F0R2_FB10_Pos (10U)
4307#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
4308#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
4309#define CAN_F0R2_FB11_Pos (11U)
4310#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
4311#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
4312#define CAN_F0R2_FB12_Pos (12U)
4313#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
4314#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
4315#define CAN_F0R2_FB13_Pos (13U)
4316#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
4317#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
4318#define CAN_F0R2_FB14_Pos (14U)
4319#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
4320#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
4321#define CAN_F0R2_FB15_Pos (15U)
4322#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
4323#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
4324#define CAN_F0R2_FB16_Pos (16U)
4325#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
4326#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
4327#define CAN_F0R2_FB17_Pos (17U)
4328#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
4329#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
4330#define CAN_F0R2_FB18_Pos (18U)
4331#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
4332#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
4333#define CAN_F0R2_FB19_Pos (19U)
4334#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
4335#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
4336#define CAN_F0R2_FB20_Pos (20U)
4337#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
4338#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
4339#define CAN_F0R2_FB21_Pos (21U)
4340#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
4341#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
4342#define CAN_F0R2_FB22_Pos (22U)
4343#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
4344#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
4345#define CAN_F0R2_FB23_Pos (23U)
4346#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
4347#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
4348#define CAN_F0R2_FB24_Pos (24U)
4349#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
4350#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
4351#define CAN_F0R2_FB25_Pos (25U)
4352#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
4353#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
4354#define CAN_F0R2_FB26_Pos (26U)
4355#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
4356#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
4357#define CAN_F0R2_FB27_Pos (27U)
4358#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
4359#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
4360#define CAN_F0R2_FB28_Pos (28U)
4361#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
4362#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
4363#define CAN_F0R2_FB29_Pos (29U)
4364#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
4365#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
4366#define CAN_F0R2_FB30_Pos (30U)
4367#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
4368#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
4369#define CAN_F0R2_FB31_Pos (31U)
4370#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
4371#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
4372
4373/******************* Bit definition for CAN_F1R2 register *******************/
4374#define CAN_F1R2_FB0_Pos (0U)
4375#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
4376#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
4377#define CAN_F1R2_FB1_Pos (1U)
4378#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
4379#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
4380#define CAN_F1R2_FB2_Pos (2U)
4381#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
4382#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
4383#define CAN_F1R2_FB3_Pos (3U)
4384#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
4385#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
4386#define CAN_F1R2_FB4_Pos (4U)
4387#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
4388#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
4389#define CAN_F1R2_FB5_Pos (5U)
4390#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
4391#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
4392#define CAN_F1R2_FB6_Pos (6U)
4393#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
4394#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
4395#define CAN_F1R2_FB7_Pos (7U)
4396#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
4397#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
4398#define CAN_F1R2_FB8_Pos (8U)
4399#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
4400#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
4401#define CAN_F1R2_FB9_Pos (9U)
4402#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
4403#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
4404#define CAN_F1R2_FB10_Pos (10U)
4405#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
4406#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
4407#define CAN_F1R2_FB11_Pos (11U)
4408#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
4409#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
4410#define CAN_F1R2_FB12_Pos (12U)
4411#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
4412#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
4413#define CAN_F1R2_FB13_Pos (13U)
4414#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
4415#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
4416#define CAN_F1R2_FB14_Pos (14U)
4417#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
4418#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
4419#define CAN_F1R2_FB15_Pos (15U)
4420#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
4421#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
4422#define CAN_F1R2_FB16_Pos (16U)
4423#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
4424#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
4425#define CAN_F1R2_FB17_Pos (17U)
4426#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
4427#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
4428#define CAN_F1R2_FB18_Pos (18U)
4429#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
4430#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
4431#define CAN_F1R2_FB19_Pos (19U)
4432#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
4433#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
4434#define CAN_F1R2_FB20_Pos (20U)
4435#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
4436#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
4437#define CAN_F1R2_FB21_Pos (21U)
4438#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
4439#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
4440#define CAN_F1R2_FB22_Pos (22U)
4441#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
4442#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
4443#define CAN_F1R2_FB23_Pos (23U)
4444#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
4445#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
4446#define CAN_F1R2_FB24_Pos (24U)
4447#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
4448#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
4449#define CAN_F1R2_FB25_Pos (25U)
4450#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
4451#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
4452#define CAN_F1R2_FB26_Pos (26U)
4453#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
4454#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
4455#define CAN_F1R2_FB27_Pos (27U)
4456#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
4457#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
4458#define CAN_F1R2_FB28_Pos (28U)
4459#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
4460#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
4461#define CAN_F1R2_FB29_Pos (29U)
4462#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
4463#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
4464#define CAN_F1R2_FB30_Pos (30U)
4465#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
4466#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
4467#define CAN_F1R2_FB31_Pos (31U)
4468#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
4469#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
4470
4471/******************* Bit definition for CAN_F2R2 register *******************/
4472#define CAN_F2R2_FB0_Pos (0U)
4473#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
4474#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
4475#define CAN_F2R2_FB1_Pos (1U)
4476#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
4477#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
4478#define CAN_F2R2_FB2_Pos (2U)
4479#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
4480#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
4481#define CAN_F2R2_FB3_Pos (3U)
4482#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
4483#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
4484#define CAN_F2R2_FB4_Pos (4U)
4485#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
4486#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
4487#define CAN_F2R2_FB5_Pos (5U)
4488#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
4489#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
4490#define CAN_F2R2_FB6_Pos (6U)
4491#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
4492#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
4493#define CAN_F2R2_FB7_Pos (7U)
4494#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
4495#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
4496#define CAN_F2R2_FB8_Pos (8U)
4497#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
4498#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
4499#define CAN_F2R2_FB9_Pos (9U)
4500#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
4501#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
4502#define CAN_F2R2_FB10_Pos (10U)
4503#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
4504#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
4505#define CAN_F2R2_FB11_Pos (11U)
4506#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
4507#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
4508#define CAN_F2R2_FB12_Pos (12U)
4509#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
4510#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
4511#define CAN_F2R2_FB13_Pos (13U)
4512#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
4513#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
4514#define CAN_F2R2_FB14_Pos (14U)
4515#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
4516#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
4517#define CAN_F2R2_FB15_Pos (15U)
4518#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
4519#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
4520#define CAN_F2R2_FB16_Pos (16U)
4521#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
4522#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
4523#define CAN_F2R2_FB17_Pos (17U)
4524#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
4525#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
4526#define CAN_F2R2_FB18_Pos (18U)
4527#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
4528#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
4529#define CAN_F2R2_FB19_Pos (19U)
4530#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
4531#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
4532#define CAN_F2R2_FB20_Pos (20U)
4533#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
4534#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
4535#define CAN_F2R2_FB21_Pos (21U)
4536#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
4537#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
4538#define CAN_F2R2_FB22_Pos (22U)
4539#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
4540#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
4541#define CAN_F2R2_FB23_Pos (23U)
4542#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
4543#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
4544#define CAN_F2R2_FB24_Pos (24U)
4545#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
4546#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
4547#define CAN_F2R2_FB25_Pos (25U)
4548#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
4549#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
4550#define CAN_F2R2_FB26_Pos (26U)
4551#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
4552#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
4553#define CAN_F2R2_FB27_Pos (27U)
4554#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
4555#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
4556#define CAN_F2R2_FB28_Pos (28U)
4557#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
4558#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
4559#define CAN_F2R2_FB29_Pos (29U)
4560#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
4561#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
4562#define CAN_F2R2_FB30_Pos (30U)
4563#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
4564#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
4565#define CAN_F2R2_FB31_Pos (31U)
4566#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
4567#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
4568
4569/******************* Bit definition for CAN_F3R2 register *******************/
4570#define CAN_F3R2_FB0_Pos (0U)
4571#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
4572#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
4573#define CAN_F3R2_FB1_Pos (1U)
4574#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
4575#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
4576#define CAN_F3R2_FB2_Pos (2U)
4577#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
4578#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
4579#define CAN_F3R2_FB3_Pos (3U)
4580#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
4581#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
4582#define CAN_F3R2_FB4_Pos (4U)
4583#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
4584#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
4585#define CAN_F3R2_FB5_Pos (5U)
4586#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
4587#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
4588#define CAN_F3R2_FB6_Pos (6U)
4589#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
4590#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
4591#define CAN_F3R2_FB7_Pos (7U)
4592#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
4593#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
4594#define CAN_F3R2_FB8_Pos (8U)
4595#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
4596#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
4597#define CAN_F3R2_FB9_Pos (9U)
4598#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
4599#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
4600#define CAN_F3R2_FB10_Pos (10U)
4601#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
4602#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
4603#define CAN_F3R2_FB11_Pos (11U)
4604#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
4605#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
4606#define CAN_F3R2_FB12_Pos (12U)
4607#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
4608#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
4609#define CAN_F3R2_FB13_Pos (13U)
4610#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
4611#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
4612#define CAN_F3R2_FB14_Pos (14U)
4613#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
4614#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
4615#define CAN_F3R2_FB15_Pos (15U)
4616#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
4617#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
4618#define CAN_F3R2_FB16_Pos (16U)
4619#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
4620#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
4621#define CAN_F3R2_FB17_Pos (17U)
4622#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
4623#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
4624#define CAN_F3R2_FB18_Pos (18U)
4625#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
4626#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
4627#define CAN_F3R2_FB19_Pos (19U)
4628#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
4629#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
4630#define CAN_F3R2_FB20_Pos (20U)
4631#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
4632#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
4633#define CAN_F3R2_FB21_Pos (21U)
4634#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
4635#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
4636#define CAN_F3R2_FB22_Pos (22U)
4637#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
4638#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
4639#define CAN_F3R2_FB23_Pos (23U)
4640#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
4641#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
4642#define CAN_F3R2_FB24_Pos (24U)
4643#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
4644#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
4645#define CAN_F3R2_FB25_Pos (25U)
4646#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
4647#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
4648#define CAN_F3R2_FB26_Pos (26U)
4649#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
4650#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
4651#define CAN_F3R2_FB27_Pos (27U)
4652#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
4653#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
4654#define CAN_F3R2_FB28_Pos (28U)
4655#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
4656#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
4657#define CAN_F3R2_FB29_Pos (29U)
4658#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
4659#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
4660#define CAN_F3R2_FB30_Pos (30U)
4661#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
4662#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
4663#define CAN_F3R2_FB31_Pos (31U)
4664#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
4665#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
4666
4667/******************* Bit definition for CAN_F4R2 register *******************/
4668#define CAN_F4R2_FB0_Pos (0U)
4669#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
4670#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
4671#define CAN_F4R2_FB1_Pos (1U)
4672#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
4673#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
4674#define CAN_F4R2_FB2_Pos (2U)
4675#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
4676#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
4677#define CAN_F4R2_FB3_Pos (3U)
4678#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
4679#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
4680#define CAN_F4R2_FB4_Pos (4U)
4681#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
4682#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
4683#define CAN_F4R2_FB5_Pos (5U)
4684#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
4685#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
4686#define CAN_F4R2_FB6_Pos (6U)
4687#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
4688#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
4689#define CAN_F4R2_FB7_Pos (7U)
4690#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
4691#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
4692#define CAN_F4R2_FB8_Pos (8U)
4693#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
4694#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
4695#define CAN_F4R2_FB9_Pos (9U)
4696#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
4697#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
4698#define CAN_F4R2_FB10_Pos (10U)
4699#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
4700#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
4701#define CAN_F4R2_FB11_Pos (11U)
4702#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
4703#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
4704#define CAN_F4R2_FB12_Pos (12U)
4705#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
4706#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
4707#define CAN_F4R2_FB13_Pos (13U)
4708#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
4709#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
4710#define CAN_F4R2_FB14_Pos (14U)
4711#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
4712#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
4713#define CAN_F4R2_FB15_Pos (15U)
4714#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
4715#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
4716#define CAN_F4R2_FB16_Pos (16U)
4717#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
4718#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
4719#define CAN_F4R2_FB17_Pos (17U)
4720#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
4721#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
4722#define CAN_F4R2_FB18_Pos (18U)
4723#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
4724#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
4725#define CAN_F4R2_FB19_Pos (19U)
4726#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
4727#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
4728#define CAN_F4R2_FB20_Pos (20U)
4729#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
4730#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
4731#define CAN_F4R2_FB21_Pos (21U)
4732#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
4733#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
4734#define CAN_F4R2_FB22_Pos (22U)
4735#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
4736#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
4737#define CAN_F4R2_FB23_Pos (23U)
4738#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
4739#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
4740#define CAN_F4R2_FB24_Pos (24U)
4741#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
4742#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
4743#define CAN_F4R2_FB25_Pos (25U)
4744#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
4745#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
4746#define CAN_F4R2_FB26_Pos (26U)
4747#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
4748#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
4749#define CAN_F4R2_FB27_Pos (27U)
4750#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
4751#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
4752#define CAN_F4R2_FB28_Pos (28U)
4753#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
4754#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
4755#define CAN_F4R2_FB29_Pos (29U)
4756#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
4757#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
4758#define CAN_F4R2_FB30_Pos (30U)
4759#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
4760#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
4761#define CAN_F4R2_FB31_Pos (31U)
4762#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
4763#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
4764
4765/******************* Bit definition for CAN_F5R2 register *******************/
4766#define CAN_F5R2_FB0_Pos (0U)
4767#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
4768#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
4769#define CAN_F5R2_FB1_Pos (1U)
4770#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
4771#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
4772#define CAN_F5R2_FB2_Pos (2U)
4773#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
4774#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
4775#define CAN_F5R2_FB3_Pos (3U)
4776#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
4777#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
4778#define CAN_F5R2_FB4_Pos (4U)
4779#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
4780#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
4781#define CAN_F5R2_FB5_Pos (5U)
4782#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
4783#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
4784#define CAN_F5R2_FB6_Pos (6U)
4785#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
4786#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
4787#define CAN_F5R2_FB7_Pos (7U)
4788#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
4789#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
4790#define CAN_F5R2_FB8_Pos (8U)
4791#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
4792#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
4793#define CAN_F5R2_FB9_Pos (9U)
4794#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
4795#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
4796#define CAN_F5R2_FB10_Pos (10U)
4797#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
4798#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
4799#define CAN_F5R2_FB11_Pos (11U)
4800#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
4801#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
4802#define CAN_F5R2_FB12_Pos (12U)
4803#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
4804#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
4805#define CAN_F5R2_FB13_Pos (13U)
4806#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
4807#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
4808#define CAN_F5R2_FB14_Pos (14U)
4809#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
4810#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
4811#define CAN_F5R2_FB15_Pos (15U)
4812#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
4813#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
4814#define CAN_F5R2_FB16_Pos (16U)
4815#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
4816#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
4817#define CAN_F5R2_FB17_Pos (17U)
4818#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
4819#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
4820#define CAN_F5R2_FB18_Pos (18U)
4821#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
4822#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
4823#define CAN_F5R2_FB19_Pos (19U)
4824#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
4825#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
4826#define CAN_F5R2_FB20_Pos (20U)
4827#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
4828#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
4829#define CAN_F5R2_FB21_Pos (21U)
4830#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
4831#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
4832#define CAN_F5R2_FB22_Pos (22U)
4833#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
4834#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
4835#define CAN_F5R2_FB23_Pos (23U)
4836#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
4837#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
4838#define CAN_F5R2_FB24_Pos (24U)
4839#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
4840#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
4841#define CAN_F5R2_FB25_Pos (25U)
4842#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
4843#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
4844#define CAN_F5R2_FB26_Pos (26U)
4845#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
4846#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
4847#define CAN_F5R2_FB27_Pos (27U)
4848#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
4849#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
4850#define CAN_F5R2_FB28_Pos (28U)
4851#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
4852#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
4853#define CAN_F5R2_FB29_Pos (29U)
4854#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
4855#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
4856#define CAN_F5R2_FB30_Pos (30U)
4857#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
4858#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
4859#define CAN_F5R2_FB31_Pos (31U)
4860#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
4861#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
4862
4863/******************* Bit definition for CAN_F6R2 register *******************/
4864#define CAN_F6R2_FB0_Pos (0U)
4865#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
4866#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
4867#define CAN_F6R2_FB1_Pos (1U)
4868#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
4869#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
4870#define CAN_F6R2_FB2_Pos (2U)
4871#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
4872#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
4873#define CAN_F6R2_FB3_Pos (3U)
4874#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
4875#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
4876#define CAN_F6R2_FB4_Pos (4U)
4877#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
4878#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
4879#define CAN_F6R2_FB5_Pos (5U)
4880#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
4881#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
4882#define CAN_F6R2_FB6_Pos (6U)
4883#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
4884#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
4885#define CAN_F6R2_FB7_Pos (7U)
4886#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
4887#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
4888#define CAN_F6R2_FB8_Pos (8U)
4889#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
4890#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
4891#define CAN_F6R2_FB9_Pos (9U)
4892#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
4893#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
4894#define CAN_F6R2_FB10_Pos (10U)
4895#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
4896#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
4897#define CAN_F6R2_FB11_Pos (11U)
4898#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
4899#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
4900#define CAN_F6R2_FB12_Pos (12U)
4901#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
4902#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
4903#define CAN_F6R2_FB13_Pos (13U)
4904#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
4905#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
4906#define CAN_F6R2_FB14_Pos (14U)
4907#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
4908#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
4909#define CAN_F6R2_FB15_Pos (15U)
4910#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
4911#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
4912#define CAN_F6R2_FB16_Pos (16U)
4913#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
4914#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
4915#define CAN_F6R2_FB17_Pos (17U)
4916#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
4917#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
4918#define CAN_F6R2_FB18_Pos (18U)
4919#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
4920#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
4921#define CAN_F6R2_FB19_Pos (19U)
4922#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
4923#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
4924#define CAN_F6R2_FB20_Pos (20U)
4925#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
4926#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
4927#define CAN_F6R2_FB21_Pos (21U)
4928#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
4929#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
4930#define CAN_F6R2_FB22_Pos (22U)
4931#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
4932#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
4933#define CAN_F6R2_FB23_Pos (23U)
4934#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
4935#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
4936#define CAN_F6R2_FB24_Pos (24U)
4937#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
4938#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
4939#define CAN_F6R2_FB25_Pos (25U)
4940#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
4941#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
4942#define CAN_F6R2_FB26_Pos (26U)
4943#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
4944#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
4945#define CAN_F6R2_FB27_Pos (27U)
4946#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
4947#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
4948#define CAN_F6R2_FB28_Pos (28U)
4949#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
4950#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
4951#define CAN_F6R2_FB29_Pos (29U)
4952#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
4953#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
4954#define CAN_F6R2_FB30_Pos (30U)
4955#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
4956#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
4957#define CAN_F6R2_FB31_Pos (31U)
4958#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
4959#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
4960
4961/******************* Bit definition for CAN_F7R2 register *******************/
4962#define CAN_F7R2_FB0_Pos (0U)
4963#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
4964#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
4965#define CAN_F7R2_FB1_Pos (1U)
4966#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
4967#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
4968#define CAN_F7R2_FB2_Pos (2U)
4969#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
4970#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
4971#define CAN_F7R2_FB3_Pos (3U)
4972#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
4973#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
4974#define CAN_F7R2_FB4_Pos (4U)
4975#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
4976#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
4977#define CAN_F7R2_FB5_Pos (5U)
4978#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
4979#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
4980#define CAN_F7R2_FB6_Pos (6U)
4981#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
4982#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
4983#define CAN_F7R2_FB7_Pos (7U)
4984#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
4985#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
4986#define CAN_F7R2_FB8_Pos (8U)
4987#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
4988#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
4989#define CAN_F7R2_FB9_Pos (9U)
4990#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
4991#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
4992#define CAN_F7R2_FB10_Pos (10U)
4993#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
4994#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
4995#define CAN_F7R2_FB11_Pos (11U)
4996#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
4997#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
4998#define CAN_F7R2_FB12_Pos (12U)
4999#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
5000#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
5001#define CAN_F7R2_FB13_Pos (13U)
5002#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
5003#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
5004#define CAN_F7R2_FB14_Pos (14U)
5005#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
5006#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
5007#define CAN_F7R2_FB15_Pos (15U)
5008#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
5009#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
5010#define CAN_F7R2_FB16_Pos (16U)
5011#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
5012#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
5013#define CAN_F7R2_FB17_Pos (17U)
5014#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
5015#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
5016#define CAN_F7R2_FB18_Pos (18U)
5017#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
5018#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
5019#define CAN_F7R2_FB19_Pos (19U)
5020#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
5021#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
5022#define CAN_F7R2_FB20_Pos (20U)
5023#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
5024#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
5025#define CAN_F7R2_FB21_Pos (21U)
5026#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
5027#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
5028#define CAN_F7R2_FB22_Pos (22U)
5029#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
5030#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
5031#define CAN_F7R2_FB23_Pos (23U)
5032#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
5033#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
5034#define CAN_F7R2_FB24_Pos (24U)
5035#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
5036#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
5037#define CAN_F7R2_FB25_Pos (25U)
5038#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
5039#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
5040#define CAN_F7R2_FB26_Pos (26U)
5041#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
5042#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
5043#define CAN_F7R2_FB27_Pos (27U)
5044#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
5045#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
5046#define CAN_F7R2_FB28_Pos (28U)
5047#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
5048#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
5049#define CAN_F7R2_FB29_Pos (29U)
5050#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
5051#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
5052#define CAN_F7R2_FB30_Pos (30U)
5053#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
5054#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
5055#define CAN_F7R2_FB31_Pos (31U)
5056#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
5057#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
5058
5059/******************* Bit definition for CAN_F8R2 register *******************/
5060#define CAN_F8R2_FB0_Pos (0U)
5061#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
5062#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
5063#define CAN_F8R2_FB1_Pos (1U)
5064#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
5065#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
5066#define CAN_F8R2_FB2_Pos (2U)
5067#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
5068#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
5069#define CAN_F8R2_FB3_Pos (3U)
5070#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
5071#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
5072#define CAN_F8R2_FB4_Pos (4U)
5073#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
5074#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
5075#define CAN_F8R2_FB5_Pos (5U)
5076#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
5077#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
5078#define CAN_F8R2_FB6_Pos (6U)
5079#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
5080#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
5081#define CAN_F8R2_FB7_Pos (7U)
5082#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
5083#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
5084#define CAN_F8R2_FB8_Pos (8U)
5085#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
5086#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
5087#define CAN_F8R2_FB9_Pos (9U)
5088#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
5089#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
5090#define CAN_F8R2_FB10_Pos (10U)
5091#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
5092#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
5093#define CAN_F8R2_FB11_Pos (11U)
5094#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
5095#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
5096#define CAN_F8R2_FB12_Pos (12U)
5097#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
5098#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
5099#define CAN_F8R2_FB13_Pos (13U)
5100#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
5101#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
5102#define CAN_F8R2_FB14_Pos (14U)
5103#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
5104#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
5105#define CAN_F8R2_FB15_Pos (15U)
5106#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
5107#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
5108#define CAN_F8R2_FB16_Pos (16U)
5109#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
5110#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
5111#define CAN_F8R2_FB17_Pos (17U)
5112#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
5113#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
5114#define CAN_F8R2_FB18_Pos (18U)
5115#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
5116#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
5117#define CAN_F8R2_FB19_Pos (19U)
5118#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
5119#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
5120#define CAN_F8R2_FB20_Pos (20U)
5121#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
5122#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
5123#define CAN_F8R2_FB21_Pos (21U)
5124#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
5125#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
5126#define CAN_F8R2_FB22_Pos (22U)
5127#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
5128#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
5129#define CAN_F8R2_FB23_Pos (23U)
5130#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
5131#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
5132#define CAN_F8R2_FB24_Pos (24U)
5133#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
5134#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
5135#define CAN_F8R2_FB25_Pos (25U)
5136#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
5137#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
5138#define CAN_F8R2_FB26_Pos (26U)
5139#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
5140#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
5141#define CAN_F8R2_FB27_Pos (27U)
5142#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
5143#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
5144#define CAN_F8R2_FB28_Pos (28U)
5145#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
5146#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
5147#define CAN_F8R2_FB29_Pos (29U)
5148#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
5149#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
5150#define CAN_F8R2_FB30_Pos (30U)
5151#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
5152#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
5153#define CAN_F8R2_FB31_Pos (31U)
5154#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
5155#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
5156
5157/******************* Bit definition for CAN_F9R2 register *******************/
5158#define CAN_F9R2_FB0_Pos (0U)
5159#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
5160#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
5161#define CAN_F9R2_FB1_Pos (1U)
5162#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
5163#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
5164#define CAN_F9R2_FB2_Pos (2U)
5165#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
5166#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
5167#define CAN_F9R2_FB3_Pos (3U)
5168#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
5169#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
5170#define CAN_F9R2_FB4_Pos (4U)
5171#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
5172#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
5173#define CAN_F9R2_FB5_Pos (5U)
5174#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
5175#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
5176#define CAN_F9R2_FB6_Pos (6U)
5177#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
5178#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
5179#define CAN_F9R2_FB7_Pos (7U)
5180#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
5181#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
5182#define CAN_F9R2_FB8_Pos (8U)
5183#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
5184#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
5185#define CAN_F9R2_FB9_Pos (9U)
5186#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
5187#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
5188#define CAN_F9R2_FB10_Pos (10U)
5189#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
5190#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
5191#define CAN_F9R2_FB11_Pos (11U)
5192#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
5193#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
5194#define CAN_F9R2_FB12_Pos (12U)
5195#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
5196#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
5197#define CAN_F9R2_FB13_Pos (13U)
5198#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
5199#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
5200#define CAN_F9R2_FB14_Pos (14U)
5201#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
5202#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
5203#define CAN_F9R2_FB15_Pos (15U)
5204#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
5205#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
5206#define CAN_F9R2_FB16_Pos (16U)
5207#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
5208#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
5209#define CAN_F9R2_FB17_Pos (17U)
5210#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
5211#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
5212#define CAN_F9R2_FB18_Pos (18U)
5213#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
5214#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
5215#define CAN_F9R2_FB19_Pos (19U)
5216#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
5217#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
5218#define CAN_F9R2_FB20_Pos (20U)
5219#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
5220#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
5221#define CAN_F9R2_FB21_Pos (21U)
5222#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
5223#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
5224#define CAN_F9R2_FB22_Pos (22U)
5225#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
5226#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
5227#define CAN_F9R2_FB23_Pos (23U)
5228#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
5229#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
5230#define CAN_F9R2_FB24_Pos (24U)
5231#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
5232#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
5233#define CAN_F9R2_FB25_Pos (25U)
5234#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
5235#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
5236#define CAN_F9R2_FB26_Pos (26U)
5237#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
5238#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
5239#define CAN_F9R2_FB27_Pos (27U)
5240#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
5241#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
5242#define CAN_F9R2_FB28_Pos (28U)
5243#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
5244#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
5245#define CAN_F9R2_FB29_Pos (29U)
5246#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
5247#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
5248#define CAN_F9R2_FB30_Pos (30U)
5249#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
5250#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
5251#define CAN_F9R2_FB31_Pos (31U)
5252#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
5253#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
5254
5255/******************* Bit definition for CAN_F10R2 register ******************/
5256#define CAN_F10R2_FB0_Pos (0U)
5257#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
5258#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
5259#define CAN_F10R2_FB1_Pos (1U)
5260#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
5261#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
5262#define CAN_F10R2_FB2_Pos (2U)
5263#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
5264#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
5265#define CAN_F10R2_FB3_Pos (3U)
5266#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
5267#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
5268#define CAN_F10R2_FB4_Pos (4U)
5269#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
5270#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
5271#define CAN_F10R2_FB5_Pos (5U)
5272#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
5273#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
5274#define CAN_F10R2_FB6_Pos (6U)
5275#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
5276#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
5277#define CAN_F10R2_FB7_Pos (7U)
5278#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
5279#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
5280#define CAN_F10R2_FB8_Pos (8U)
5281#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
5282#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
5283#define CAN_F10R2_FB9_Pos (9U)
5284#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
5285#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
5286#define CAN_F10R2_FB10_Pos (10U)
5287#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
5288#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
5289#define CAN_F10R2_FB11_Pos (11U)
5290#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
5291#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
5292#define CAN_F10R2_FB12_Pos (12U)
5293#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
5294#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
5295#define CAN_F10R2_FB13_Pos (13U)
5296#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
5297#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
5298#define CAN_F10R2_FB14_Pos (14U)
5299#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
5300#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
5301#define CAN_F10R2_FB15_Pos (15U)
5302#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
5303#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
5304#define CAN_F10R2_FB16_Pos (16U)
5305#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
5306#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
5307#define CAN_F10R2_FB17_Pos (17U)
5308#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
5309#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
5310#define CAN_F10R2_FB18_Pos (18U)
5311#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
5312#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
5313#define CAN_F10R2_FB19_Pos (19U)
5314#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
5315#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
5316#define CAN_F10R2_FB20_Pos (20U)
5317#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
5318#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
5319#define CAN_F10R2_FB21_Pos (21U)
5320#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
5321#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
5322#define CAN_F10R2_FB22_Pos (22U)
5323#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
5324#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
5325#define CAN_F10R2_FB23_Pos (23U)
5326#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
5327#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
5328#define CAN_F10R2_FB24_Pos (24U)
5329#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
5330#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
5331#define CAN_F10R2_FB25_Pos (25U)
5332#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
5333#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
5334#define CAN_F10R2_FB26_Pos (26U)
5335#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
5336#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
5337#define CAN_F10R2_FB27_Pos (27U)
5338#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
5339#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
5340#define CAN_F10R2_FB28_Pos (28U)
5341#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
5342#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
5343#define CAN_F10R2_FB29_Pos (29U)
5344#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
5345#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
5346#define CAN_F10R2_FB30_Pos (30U)
5347#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
5348#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
5349#define CAN_F10R2_FB31_Pos (31U)
5350#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
5351#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
5352
5353/******************* Bit definition for CAN_F11R2 register ******************/
5354#define CAN_F11R2_FB0_Pos (0U)
5355#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
5356#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
5357#define CAN_F11R2_FB1_Pos (1U)
5358#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
5359#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
5360#define CAN_F11R2_FB2_Pos (2U)
5361#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
5362#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
5363#define CAN_F11R2_FB3_Pos (3U)
5364#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
5365#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
5366#define CAN_F11R2_FB4_Pos (4U)
5367#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
5368#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
5369#define CAN_F11R2_FB5_Pos (5U)
5370#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
5371#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
5372#define CAN_F11R2_FB6_Pos (6U)
5373#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
5374#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
5375#define CAN_F11R2_FB7_Pos (7U)
5376#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
5377#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
5378#define CAN_F11R2_FB8_Pos (8U)
5379#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
5380#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
5381#define CAN_F11R2_FB9_Pos (9U)
5382#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
5383#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
5384#define CAN_F11R2_FB10_Pos (10U)
5385#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
5386#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
5387#define CAN_F11R2_FB11_Pos (11U)
5388#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
5389#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
5390#define CAN_F11R2_FB12_Pos (12U)
5391#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
5392#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
5393#define CAN_F11R2_FB13_Pos (13U)
5394#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
5395#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
5396#define CAN_F11R2_FB14_Pos (14U)
5397#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
5398#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
5399#define CAN_F11R2_FB15_Pos (15U)
5400#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
5401#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
5402#define CAN_F11R2_FB16_Pos (16U)
5403#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
5404#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
5405#define CAN_F11R2_FB17_Pos (17U)
5406#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
5407#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
5408#define CAN_F11R2_FB18_Pos (18U)
5409#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
5410#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
5411#define CAN_F11R2_FB19_Pos (19U)
5412#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
5413#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
5414#define CAN_F11R2_FB20_Pos (20U)
5415#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
5416#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
5417#define CAN_F11R2_FB21_Pos (21U)
5418#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
5419#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
5420#define CAN_F11R2_FB22_Pos (22U)
5421#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
5422#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
5423#define CAN_F11R2_FB23_Pos (23U)
5424#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
5425#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
5426#define CAN_F11R2_FB24_Pos (24U)
5427#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
5428#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
5429#define CAN_F11R2_FB25_Pos (25U)
5430#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
5431#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
5432#define CAN_F11R2_FB26_Pos (26U)
5433#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
5434#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
5435#define CAN_F11R2_FB27_Pos (27U)
5436#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
5437#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
5438#define CAN_F11R2_FB28_Pos (28U)
5439#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
5440#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
5441#define CAN_F11R2_FB29_Pos (29U)
5442#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
5443#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
5444#define CAN_F11R2_FB30_Pos (30U)
5445#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
5446#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
5447#define CAN_F11R2_FB31_Pos (31U)
5448#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
5449#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
5450
5451/******************* Bit definition for CAN_F12R2 register ******************/
5452#define CAN_F12R2_FB0_Pos (0U)
5453#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
5454#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
5455#define CAN_F12R2_FB1_Pos (1U)
5456#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
5457#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
5458#define CAN_F12R2_FB2_Pos (2U)
5459#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
5460#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
5461#define CAN_F12R2_FB3_Pos (3U)
5462#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
5463#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
5464#define CAN_F12R2_FB4_Pos (4U)
5465#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
5466#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
5467#define CAN_F12R2_FB5_Pos (5U)
5468#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
5469#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
5470#define CAN_F12R2_FB6_Pos (6U)
5471#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
5472#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
5473#define CAN_F12R2_FB7_Pos (7U)
5474#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
5475#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
5476#define CAN_F12R2_FB8_Pos (8U)
5477#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
5478#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
5479#define CAN_F12R2_FB9_Pos (9U)
5480#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
5481#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
5482#define CAN_F12R2_FB10_Pos (10U)
5483#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
5484#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
5485#define CAN_F12R2_FB11_Pos (11U)
5486#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
5487#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
5488#define CAN_F12R2_FB12_Pos (12U)
5489#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
5490#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
5491#define CAN_F12R2_FB13_Pos (13U)
5492#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
5493#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
5494#define CAN_F12R2_FB14_Pos (14U)
5495#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
5496#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
5497#define CAN_F12R2_FB15_Pos (15U)
5498#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
5499#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
5500#define CAN_F12R2_FB16_Pos (16U)
5501#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
5502#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
5503#define CAN_F12R2_FB17_Pos (17U)
5504#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
5505#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
5506#define CAN_F12R2_FB18_Pos (18U)
5507#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
5508#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
5509#define CAN_F12R2_FB19_Pos (19U)
5510#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
5511#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
5512#define CAN_F12R2_FB20_Pos (20U)
5513#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
5514#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
5515#define CAN_F12R2_FB21_Pos (21U)
5516#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
5517#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
5518#define CAN_F12R2_FB22_Pos (22U)
5519#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
5520#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
5521#define CAN_F12R2_FB23_Pos (23U)
5522#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
5523#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
5524#define CAN_F12R2_FB24_Pos (24U)
5525#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
5526#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
5527#define CAN_F12R2_FB25_Pos (25U)
5528#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
5529#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
5530#define CAN_F12R2_FB26_Pos (26U)
5531#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
5532#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
5533#define CAN_F12R2_FB27_Pos (27U)
5534#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
5535#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
5536#define CAN_F12R2_FB28_Pos (28U)
5537#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
5538#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
5539#define CAN_F12R2_FB29_Pos (29U)
5540#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
5541#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
5542#define CAN_F12R2_FB30_Pos (30U)
5543#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
5544#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
5545#define CAN_F12R2_FB31_Pos (31U)
5546#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
5547#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
5548
5549/******************* Bit definition for CAN_F13R2 register ******************/
5550#define CAN_F13R2_FB0_Pos (0U)
5551#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
5552#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
5553#define CAN_F13R2_FB1_Pos (1U)
5554#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
5555#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
5556#define CAN_F13R2_FB2_Pos (2U)
5557#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
5558#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
5559#define CAN_F13R2_FB3_Pos (3U)
5560#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
5561#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
5562#define CAN_F13R2_FB4_Pos (4U)
5563#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
5564#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
5565#define CAN_F13R2_FB5_Pos (5U)
5566#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
5567#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
5568#define CAN_F13R2_FB6_Pos (6U)
5569#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
5570#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
5571#define CAN_F13R2_FB7_Pos (7U)
5572#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
5573#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
5574#define CAN_F13R2_FB8_Pos (8U)
5575#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
5576#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
5577#define CAN_F13R2_FB9_Pos (9U)
5578#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
5579#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
5580#define CAN_F13R2_FB10_Pos (10U)
5581#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
5582#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
5583#define CAN_F13R2_FB11_Pos (11U)
5584#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
5585#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
5586#define CAN_F13R2_FB12_Pos (12U)
5587#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
5588#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
5589#define CAN_F13R2_FB13_Pos (13U)
5590#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
5591#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
5592#define CAN_F13R2_FB14_Pos (14U)
5593#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
5594#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
5595#define CAN_F13R2_FB15_Pos (15U)
5596#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
5597#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
5598#define CAN_F13R2_FB16_Pos (16U)
5599#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
5600#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
5601#define CAN_F13R2_FB17_Pos (17U)
5602#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
5603#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
5604#define CAN_F13R2_FB18_Pos (18U)
5605#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
5606#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
5607#define CAN_F13R2_FB19_Pos (19U)
5608#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
5609#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
5610#define CAN_F13R2_FB20_Pos (20U)
5611#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
5612#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
5613#define CAN_F13R2_FB21_Pos (21U)
5614#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
5615#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
5616#define CAN_F13R2_FB22_Pos (22U)
5617#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
5618#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
5619#define CAN_F13R2_FB23_Pos (23U)
5620#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
5621#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
5622#define CAN_F13R2_FB24_Pos (24U)
5623#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
5624#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
5625#define CAN_F13R2_FB25_Pos (25U)
5626#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
5627#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
5628#define CAN_F13R2_FB26_Pos (26U)
5629#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
5630#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
5631#define CAN_F13R2_FB27_Pos (27U)
5632#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
5633#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
5634#define CAN_F13R2_FB28_Pos (28U)
5635#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
5636#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
5637#define CAN_F13R2_FB29_Pos (29U)
5638#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
5639#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
5640#define CAN_F13R2_FB30_Pos (30U)
5641#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
5642#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
5643#define CAN_F13R2_FB31_Pos (31U)
5644#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
5645#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
5646
5647/******************************************************************************/
5648/* */
5649/* CRC calculation unit */
5650/* */
5651/******************************************************************************/
5652/******************* Bit definition for CRC_DR register *********************/
5653#define CRC_DR_DR_Pos (0U)
5654#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5655#define CRC_DR_DR CRC_DR_DR_Msk
5656
5657
5658/******************* Bit definition for CRC_IDR register ********************/
5659#define CRC_IDR_IDR_Pos (0U)
5660#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
5661#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5662
5663
5664/******************** Bit definition for CRC_CR register ********************/
5665#define CRC_CR_RESET_Pos (0U)
5666#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5667#define CRC_CR_RESET CRC_CR_RESET_Msk
5668
5669/******************************************************************************/
5670/* */
5671/* Crypto Processor */
5672/* */
5673/******************************************************************************/
5674/******************* Bits definition for CRYP_CR register ********************/
5675#define CRYP_CR_ALGODIR_Pos (2U)
5676#define CRYP_CR_ALGODIR_Msk (0x1UL << CRYP_CR_ALGODIR_Pos)
5677#define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
5678
5679#define CRYP_CR_ALGOMODE_Pos (3U)
5680#define CRYP_CR_ALGOMODE_Msk (0x10007UL << CRYP_CR_ALGOMODE_Pos)
5681#define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
5682#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos)
5683#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos)
5684#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos)
5685#define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
5686#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
5687#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos)
5688#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
5689#define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
5690#define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos)
5691#define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
5692#define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
5693#define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos)
5694#define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
5695#define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
5696#define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos)
5697#define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
5698#define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
5699#define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos)
5700#define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
5701#define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
5702#define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos)
5703#define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
5704#define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
5705#define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos)
5706#define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
5707#define CRYP_CR_ALGOMODE_AES_GCM_Pos (19U)
5708#define CRYP_CR_ALGOMODE_AES_GCM_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos)
5709#define CRYP_CR_ALGOMODE_AES_GCM CRYP_CR_ALGOMODE_AES_GCM_Msk
5710#define CRYP_CR_ALGOMODE_AES_CCM_Pos (3U)
5711#define CRYP_CR_ALGOMODE_AES_CCM_Msk (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos)
5712#define CRYP_CR_ALGOMODE_AES_CCM CRYP_CR_ALGOMODE_AES_CCM_Msk
5713
5714#define CRYP_CR_DATATYPE_Pos (6U)
5715#define CRYP_CR_DATATYPE_Msk (0x3UL << CRYP_CR_DATATYPE_Pos)
5716#define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
5717#define CRYP_CR_DATATYPE_0 (0x1UL << CRYP_CR_DATATYPE_Pos)
5718#define CRYP_CR_DATATYPE_1 (0x2UL << CRYP_CR_DATATYPE_Pos)
5719#define CRYP_CR_KEYSIZE_Pos (8U)
5720#define CRYP_CR_KEYSIZE_Msk (0x3UL << CRYP_CR_KEYSIZE_Pos)
5721#define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
5722#define CRYP_CR_KEYSIZE_0 (0x1UL << CRYP_CR_KEYSIZE_Pos)
5723#define CRYP_CR_KEYSIZE_1 (0x2UL << CRYP_CR_KEYSIZE_Pos)
5724#define CRYP_CR_FFLUSH_Pos (14U)
5725#define CRYP_CR_FFLUSH_Msk (0x1UL << CRYP_CR_FFLUSH_Pos)
5726#define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
5727#define CRYP_CR_CRYPEN_Pos (15U)
5728#define CRYP_CR_CRYPEN_Msk (0x1UL << CRYP_CR_CRYPEN_Pos)
5729#define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
5730
5731#define CRYP_CR_GCM_CCMPH_Pos (16U)
5732#define CRYP_CR_GCM_CCMPH_Msk (0x3UL << CRYP_CR_GCM_CCMPH_Pos)
5733#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
5734#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos)
5735#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos)
5736#define CRYP_CR_ALGOMODE_3 0x00080000U
5737
5738/****************** Bits definition for CRYP_SR register *********************/
5739#define CRYP_SR_IFEM_Pos (0U)
5740#define CRYP_SR_IFEM_Msk (0x1UL << CRYP_SR_IFEM_Pos)
5741#define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
5742#define CRYP_SR_IFNF_Pos (1U)
5743#define CRYP_SR_IFNF_Msk (0x1UL << CRYP_SR_IFNF_Pos)
5744#define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
5745#define CRYP_SR_OFNE_Pos (2U)
5746#define CRYP_SR_OFNE_Msk (0x1UL << CRYP_SR_OFNE_Pos)
5747#define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
5748#define CRYP_SR_OFFU_Pos (3U)
5749#define CRYP_SR_OFFU_Msk (0x1UL << CRYP_SR_OFFU_Pos)
5750#define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
5751#define CRYP_SR_BUSY_Pos (4U)
5752#define CRYP_SR_BUSY_Msk (0x1UL << CRYP_SR_BUSY_Pos)
5753#define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
5754/****************** Bits definition for CRYP_DMACR register ******************/
5755#define CRYP_DMACR_DIEN_Pos (0U)
5756#define CRYP_DMACR_DIEN_Msk (0x1UL << CRYP_DMACR_DIEN_Pos)
5757#define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
5758#define CRYP_DMACR_DOEN_Pos (1U)
5759#define CRYP_DMACR_DOEN_Msk (0x1UL << CRYP_DMACR_DOEN_Pos)
5760#define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
5761/***************** Bits definition for CRYP_IMSCR register ******************/
5762#define CRYP_IMSCR_INIM_Pos (0U)
5763#define CRYP_IMSCR_INIM_Msk (0x1UL << CRYP_IMSCR_INIM_Pos)
5764#define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
5765#define CRYP_IMSCR_OUTIM_Pos (1U)
5766#define CRYP_IMSCR_OUTIM_Msk (0x1UL << CRYP_IMSCR_OUTIM_Pos)
5767#define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
5768/****************** Bits definition for CRYP_RISR register *******************/
5769#define CRYP_RISR_OUTRIS_Pos (0U)
5770#define CRYP_RISR_OUTRIS_Msk (0x1UL << CRYP_RISR_OUTRIS_Pos)
5771#define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
5772#define CRYP_RISR_INRIS_Pos (1U)
5773#define CRYP_RISR_INRIS_Msk (0x1UL << CRYP_RISR_INRIS_Pos)
5774#define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
5775/****************** Bits definition for CRYP_MISR register *******************/
5776#define CRYP_MISR_INMIS_Pos (0U)
5777#define CRYP_MISR_INMIS_Msk (0x1UL << CRYP_MISR_INMIS_Pos)
5778#define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
5779#define CRYP_MISR_OUTMIS_Pos (1U)
5780#define CRYP_MISR_OUTMIS_Msk (0x1UL << CRYP_MISR_OUTMIS_Pos)
5781#define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
5782
5783/******************************************************************************/
5784/* */
5785/* Digital to Analog Converter */
5786/* */
5787/******************************************************************************/
5788/*
5789 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
5790 */
5791#define DAC_CHANNEL2_SUPPORT
5792/******************** Bit definition for DAC_CR register ********************/
5793#define DAC_CR_EN1_Pos (0U)
5794#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
5795#define DAC_CR_EN1 DAC_CR_EN1_Msk
5796#define DAC_CR_BOFF1_Pos (1U)
5797#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
5798#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
5799#define DAC_CR_TEN1_Pos (2U)
5800#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
5801#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
5802
5803#define DAC_CR_TSEL1_Pos (3U)
5804#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
5805#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
5806#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
5807#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
5808#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
5809
5810#define DAC_CR_WAVE1_Pos (6U)
5811#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
5812#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
5813#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
5814#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
5815
5816#define DAC_CR_MAMP1_Pos (8U)
5817#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
5818#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
5819#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
5820#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
5821#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
5822#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
5823
5824#define DAC_CR_DMAEN1_Pos (12U)
5825#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
5826#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
5827#define DAC_CR_DMAUDRIE1_Pos (13U)
5828#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
5829#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
5830#define DAC_CR_EN2_Pos (16U)
5831#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
5832#define DAC_CR_EN2 DAC_CR_EN2_Msk
5833#define DAC_CR_BOFF2_Pos (17U)
5834#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
5835#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
5836#define DAC_CR_TEN2_Pos (18U)
5837#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
5838#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
5839
5840#define DAC_CR_TSEL2_Pos (19U)
5841#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
5842#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
5843#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
5844#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
5845#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
5846
5847#define DAC_CR_WAVE2_Pos (22U)
5848#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
5849#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
5850#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
5851#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
5852
5853#define DAC_CR_MAMP2_Pos (24U)
5854#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
5855#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
5856#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
5857#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
5858#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
5859#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
5860
5861#define DAC_CR_DMAEN2_Pos (28U)
5862#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
5863#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
5864#define DAC_CR_DMAUDRIE2_Pos (29U)
5865#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
5866#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
5867
5868/***************** Bit definition for DAC_SWTRIGR register ******************/
5869#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5870#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
5871#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
5872#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5873#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
5874#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
5875
5876/***************** Bit definition for DAC_DHR12R1 register ******************/
5877#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5878#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
5879#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
5880
5881/***************** Bit definition for DAC_DHR12L1 register ******************/
5882#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5883#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
5884#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
5885
5886/****************** Bit definition for DAC_DHR8R1 register ******************/
5887#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5888#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
5889#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
5890
5891/***************** Bit definition for DAC_DHR12R2 register ******************/
5892#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5893#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
5894#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
5895
5896/***************** Bit definition for DAC_DHR12L2 register ******************/
5897#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5898#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
5899#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
5900
5901/****************** Bit definition for DAC_DHR8R2 register ******************/
5902#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5903#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
5904#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
5905
5906/***************** Bit definition for DAC_DHR12RD register ******************/
5907#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5908#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
5909#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
5910#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5911#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
5912#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
5913
5914/***************** Bit definition for DAC_DHR12LD register ******************/
5915#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5916#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
5917#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
5918#define DAC_DHR12LD_DACC2DHR_Pos (20U)
5919#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
5920#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
5921
5922/****************** Bit definition for DAC_DHR8RD register ******************/
5923#define DAC_DHR8RD_DACC1DHR_Pos (0U)
5924#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
5925#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
5926#define DAC_DHR8RD_DACC2DHR_Pos (8U)
5927#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
5928#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
5929
5930/******************* Bit definition for DAC_DOR1 register *******************/
5931#define DAC_DOR1_DACC1DOR_Pos (0U)
5932#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
5933#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
5934
5935/******************* Bit definition for DAC_DOR2 register *******************/
5936#define DAC_DOR2_DACC2DOR_Pos (0U)
5937#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
5938#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
5939
5940/******************** Bit definition for DAC_SR register ********************/
5941#define DAC_SR_DMAUDR1_Pos (13U)
5942#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
5943#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
5944#define DAC_SR_DMAUDR2_Pos (29U)
5945#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
5946#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
5947
5948/******************************************************************************/
5949/* */
5950/* DCMI */
5951/* */
5952/******************************************************************************/
5953/******************** Bits definition for DCMI_CR register ******************/
5954#define DCMI_CR_CAPTURE_Pos (0U)
5955#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
5956#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5957#define DCMI_CR_CM_Pos (1U)
5958#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
5959#define DCMI_CR_CM DCMI_CR_CM_Msk
5960#define DCMI_CR_CROP_Pos (2U)
5961#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
5962#define DCMI_CR_CROP DCMI_CR_CROP_Msk
5963#define DCMI_CR_JPEG_Pos (3U)
5964#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
5965#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5966#define DCMI_CR_ESS_Pos (4U)
5967#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
5968#define DCMI_CR_ESS DCMI_CR_ESS_Msk
5969#define DCMI_CR_PCKPOL_Pos (5U)
5970#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
5971#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5972#define DCMI_CR_HSPOL_Pos (6U)
5973#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
5974#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5975#define DCMI_CR_VSPOL_Pos (7U)
5976#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
5977#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5978#define DCMI_CR_FCRC_0 0x00000100U
5979#define DCMI_CR_FCRC_1 0x00000200U
5980#define DCMI_CR_EDM_0 0x00000400U
5981#define DCMI_CR_EDM_1 0x00000800U
5982#define DCMI_CR_ENABLE_Pos (14U)
5983#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
5984#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5985
5986/******************** Bits definition for DCMI_SR register ******************/
5987#define DCMI_SR_HSYNC_Pos (0U)
5988#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
5989#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
5990#define DCMI_SR_VSYNC_Pos (1U)
5991#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
5992#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
5993#define DCMI_SR_FNE_Pos (2U)
5994#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
5995#define DCMI_SR_FNE DCMI_SR_FNE_Msk
5996
5997/******************** Bits definition for DCMI_RIS register *****************/
5998#define DCMI_RIS_FRAME_RIS_Pos (0U)
5999#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
6000#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
6001#define DCMI_RIS_OVR_RIS_Pos (1U)
6002#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
6003#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
6004#define DCMI_RIS_ERR_RIS_Pos (2U)
6005#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
6006#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
6007#define DCMI_RIS_VSYNC_RIS_Pos (3U)
6008#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
6009#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
6010#define DCMI_RIS_LINE_RIS_Pos (4U)
6011#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
6012#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
6013/* Legacy defines */
6014#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
6015#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
6016#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
6017#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
6018#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
6019#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
6020
6021/******************** Bits definition for DCMI_IER register *****************/
6022#define DCMI_IER_FRAME_IE_Pos (0U)
6023#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
6024#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
6025#define DCMI_IER_OVR_IE_Pos (1U)
6026#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
6027#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
6028#define DCMI_IER_ERR_IE_Pos (2U)
6029#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
6030#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
6031#define DCMI_IER_VSYNC_IE_Pos (3U)
6032#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
6033#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
6034#define DCMI_IER_LINE_IE_Pos (4U)
6035#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
6036#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
6037/* Legacy defines */
6038#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
6039
6040/******************** Bits definition for DCMI_MIS register *****************/
6041#define DCMI_MIS_FRAME_MIS_Pos (0U)
6042#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
6043#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
6044#define DCMI_MIS_OVR_MIS_Pos (1U)
6045#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
6046#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
6047#define DCMI_MIS_ERR_MIS_Pos (2U)
6048#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
6049#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
6050#define DCMI_MIS_VSYNC_MIS_Pos (3U)
6051#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
6052#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
6053#define DCMI_MIS_LINE_MIS_Pos (4U)
6054#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
6055#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
6056
6057/* Legacy defines */
6058#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
6059#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
6060#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
6061#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
6062#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
6063
6064/******************** Bits definition for DCMI_ICR register *****************/
6065#define DCMI_ICR_FRAME_ISC_Pos (0U)
6066#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
6067#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
6068#define DCMI_ICR_OVR_ISC_Pos (1U)
6069#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
6070#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
6071#define DCMI_ICR_ERR_ISC_Pos (2U)
6072#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
6073#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
6074#define DCMI_ICR_VSYNC_ISC_Pos (3U)
6075#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
6076#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6077#define DCMI_ICR_LINE_ISC_Pos (4U)
6078#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
6079#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6080
6081/* Legacy defines */
6082#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
6083
6084/******************** Bits definition for DCMI_ESCR register ******************/
6085#define DCMI_ESCR_FSC_Pos (0U)
6086#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
6087#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6088#define DCMI_ESCR_LSC_Pos (8U)
6089#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
6090#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6091#define DCMI_ESCR_LEC_Pos (16U)
6092#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
6093#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6094#define DCMI_ESCR_FEC_Pos (24U)
6095#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
6096#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6097
6098/******************** Bits definition for DCMI_ESUR register ******************/
6099#define DCMI_ESUR_FSU_Pos (0U)
6100#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
6101#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6102#define DCMI_ESUR_LSU_Pos (8U)
6103#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
6104#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6105#define DCMI_ESUR_LEU_Pos (16U)
6106#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
6107#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6108#define DCMI_ESUR_FEU_Pos (24U)
6109#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
6110#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6111
6112/******************** Bits definition for DCMI_CWSTRT register ******************/
6113#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6114#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
6115#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6116#define DCMI_CWSTRT_VST_Pos (16U)
6117#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
6118#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6119
6120/******************** Bits definition for DCMI_CWSIZE register ******************/
6121#define DCMI_CWSIZE_CAPCNT_Pos (0U)
6122#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
6123#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6124#define DCMI_CWSIZE_VLINE_Pos (16U)
6125#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
6126#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6127
6128/******************** Bits definition for DCMI_DR register *********************/
6129#define DCMI_DR_BYTE0_Pos (0U)
6130#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
6131#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6132#define DCMI_DR_BYTE1_Pos (8U)
6133#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
6134#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6135#define DCMI_DR_BYTE2_Pos (16U)
6136#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
6137#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6138#define DCMI_DR_BYTE3_Pos (24U)
6139#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
6140#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6141
6142/******************************************************************************/
6143/* */
6144/* DMA Controller */
6145/* */
6146/******************************************************************************/
6147/******************** Bits definition for DMA_SxCR register *****************/
6148#define DMA_SxCR_CHSEL_Pos (25U)
6149#define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos)
6150#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
6151#define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos)
6152#define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos)
6153#define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos)
6154#define DMA_SxCR_MBURST_Pos (23U)
6155#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
6156#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
6157#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
6158#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
6159#define DMA_SxCR_PBURST_Pos (21U)
6160#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
6161#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
6162#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
6163#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
6164#define DMA_SxCR_CT_Pos (19U)
6165#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
6166#define DMA_SxCR_CT DMA_SxCR_CT_Msk
6167#define DMA_SxCR_DBM_Pos (18U)
6168#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
6169#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
6170#define DMA_SxCR_PL_Pos (16U)
6171#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
6172#define DMA_SxCR_PL DMA_SxCR_PL_Msk
6173#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
6174#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
6175#define DMA_SxCR_PINCOS_Pos (15U)
6176#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
6177#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
6178#define DMA_SxCR_MSIZE_Pos (13U)
6179#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
6180#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
6181#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
6182#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
6183#define DMA_SxCR_PSIZE_Pos (11U)
6184#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
6185#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
6186#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
6187#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
6188#define DMA_SxCR_MINC_Pos (10U)
6189#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
6190#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
6191#define DMA_SxCR_PINC_Pos (9U)
6192#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
6193#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
6194#define DMA_SxCR_CIRC_Pos (8U)
6195#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
6196#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
6197#define DMA_SxCR_DIR_Pos (6U)
6198#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
6199#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
6200#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
6201#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
6202#define DMA_SxCR_PFCTRL_Pos (5U)
6203#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
6204#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
6205#define DMA_SxCR_TCIE_Pos (4U)
6206#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
6207#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
6208#define DMA_SxCR_HTIE_Pos (3U)
6209#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
6210#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
6211#define DMA_SxCR_TEIE_Pos (2U)
6212#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
6213#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
6214#define DMA_SxCR_DMEIE_Pos (1U)
6215#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
6216#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
6217#define DMA_SxCR_EN_Pos (0U)
6218#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
6219#define DMA_SxCR_EN DMA_SxCR_EN_Msk
6220
6221/* Legacy defines */
6222#define DMA_SxCR_ACK_Pos (20U)
6223#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos)
6224#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
6225
6226/******************** Bits definition for DMA_SxCNDTR register **************/
6227#define DMA_SxNDT_Pos (0U)
6228#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
6229#define DMA_SxNDT DMA_SxNDT_Msk
6230#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
6231#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
6232#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
6233#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
6234#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
6235#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
6236#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
6237#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
6238#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
6239#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
6240#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
6241#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
6242#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
6243#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
6244#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
6245#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
6246
6247/******************** Bits definition for DMA_SxFCR register ****************/
6248#define DMA_SxFCR_FEIE_Pos (7U)
6249#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
6250#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6251#define DMA_SxFCR_FS_Pos (3U)
6252#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
6253#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6254#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
6255#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
6256#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
6257#define DMA_SxFCR_DMDIS_Pos (2U)
6258#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
6259#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6260#define DMA_SxFCR_FTH_Pos (0U)
6261#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
6262#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6263#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
6264#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
6265
6266/******************** Bits definition for DMA_LISR register *****************/
6267#define DMA_LISR_TCIF3_Pos (27U)
6268#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
6269#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6270#define DMA_LISR_HTIF3_Pos (26U)
6271#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
6272#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6273#define DMA_LISR_TEIF3_Pos (25U)
6274#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
6275#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6276#define DMA_LISR_DMEIF3_Pos (24U)
6277#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
6278#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
6279#define DMA_LISR_FEIF3_Pos (22U)
6280#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
6281#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
6282#define DMA_LISR_TCIF2_Pos (21U)
6283#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
6284#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
6285#define DMA_LISR_HTIF2_Pos (20U)
6286#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
6287#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
6288#define DMA_LISR_TEIF2_Pos (19U)
6289#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
6290#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
6291#define DMA_LISR_DMEIF2_Pos (18U)
6292#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
6293#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
6294#define DMA_LISR_FEIF2_Pos (16U)
6295#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
6296#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
6297#define DMA_LISR_TCIF1_Pos (11U)
6298#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
6299#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
6300#define DMA_LISR_HTIF1_Pos (10U)
6301#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
6302#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
6303#define DMA_LISR_TEIF1_Pos (9U)
6304#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
6305#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
6306#define DMA_LISR_DMEIF1_Pos (8U)
6307#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
6308#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
6309#define DMA_LISR_FEIF1_Pos (6U)
6310#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
6311#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
6312#define DMA_LISR_TCIF0_Pos (5U)
6313#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
6314#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
6315#define DMA_LISR_HTIF0_Pos (4U)
6316#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
6317#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
6318#define DMA_LISR_TEIF0_Pos (3U)
6319#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
6320#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
6321#define DMA_LISR_DMEIF0_Pos (2U)
6322#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
6323#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
6324#define DMA_LISR_FEIF0_Pos (0U)
6325#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
6326#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6327
6328/******************** Bits definition for DMA_HISR register *****************/
6329#define DMA_HISR_TCIF7_Pos (27U)
6330#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
6331#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6332#define DMA_HISR_HTIF7_Pos (26U)
6333#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
6334#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6335#define DMA_HISR_TEIF7_Pos (25U)
6336#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
6337#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6338#define DMA_HISR_DMEIF7_Pos (24U)
6339#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
6340#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6341#define DMA_HISR_FEIF7_Pos (22U)
6342#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
6343#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6344#define DMA_HISR_TCIF6_Pos (21U)
6345#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
6346#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6347#define DMA_HISR_HTIF6_Pos (20U)
6348#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
6349#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6350#define DMA_HISR_TEIF6_Pos (19U)
6351#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
6352#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6353#define DMA_HISR_DMEIF6_Pos (18U)
6354#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
6355#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6356#define DMA_HISR_FEIF6_Pos (16U)
6357#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
6358#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6359#define DMA_HISR_TCIF5_Pos (11U)
6360#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
6361#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6362#define DMA_HISR_HTIF5_Pos (10U)
6363#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
6364#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6365#define DMA_HISR_TEIF5_Pos (9U)
6366#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
6367#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6368#define DMA_HISR_DMEIF5_Pos (8U)
6369#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
6370#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6371#define DMA_HISR_FEIF5_Pos (6U)
6372#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
6373#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6374#define DMA_HISR_TCIF4_Pos (5U)
6375#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
6376#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6377#define DMA_HISR_HTIF4_Pos (4U)
6378#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
6379#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6380#define DMA_HISR_TEIF4_Pos (3U)
6381#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
6382#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6383#define DMA_HISR_DMEIF4_Pos (2U)
6384#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
6385#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6386#define DMA_HISR_FEIF4_Pos (0U)
6387#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
6388#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6389
6390/******************** Bits definition for DMA_LIFCR register ****************/
6391#define DMA_LIFCR_CTCIF3_Pos (27U)
6392#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
6393#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6394#define DMA_LIFCR_CHTIF3_Pos (26U)
6395#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
6396#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6397#define DMA_LIFCR_CTEIF3_Pos (25U)
6398#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
6399#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6400#define DMA_LIFCR_CDMEIF3_Pos (24U)
6401#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
6402#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6403#define DMA_LIFCR_CFEIF3_Pos (22U)
6404#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
6405#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6406#define DMA_LIFCR_CTCIF2_Pos (21U)
6407#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
6408#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6409#define DMA_LIFCR_CHTIF2_Pos (20U)
6410#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
6411#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6412#define DMA_LIFCR_CTEIF2_Pos (19U)
6413#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
6414#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6415#define DMA_LIFCR_CDMEIF2_Pos (18U)
6416#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
6417#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6418#define DMA_LIFCR_CFEIF2_Pos (16U)
6419#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
6420#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6421#define DMA_LIFCR_CTCIF1_Pos (11U)
6422#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
6423#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6424#define DMA_LIFCR_CHTIF1_Pos (10U)
6425#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
6426#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6427#define DMA_LIFCR_CTEIF1_Pos (9U)
6428#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
6429#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6430#define DMA_LIFCR_CDMEIF1_Pos (8U)
6431#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
6432#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6433#define DMA_LIFCR_CFEIF1_Pos (6U)
6434#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
6435#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6436#define DMA_LIFCR_CTCIF0_Pos (5U)
6437#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
6438#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6439#define DMA_LIFCR_CHTIF0_Pos (4U)
6440#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
6441#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6442#define DMA_LIFCR_CTEIF0_Pos (3U)
6443#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
6444#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6445#define DMA_LIFCR_CDMEIF0_Pos (2U)
6446#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
6447#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6448#define DMA_LIFCR_CFEIF0_Pos (0U)
6449#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
6450#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6451
6452/******************** Bits definition for DMA_HIFCR register ****************/
6453#define DMA_HIFCR_CTCIF7_Pos (27U)
6454#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
6455#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6456#define DMA_HIFCR_CHTIF7_Pos (26U)
6457#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
6458#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6459#define DMA_HIFCR_CTEIF7_Pos (25U)
6460#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
6461#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6462#define DMA_HIFCR_CDMEIF7_Pos (24U)
6463#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
6464#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6465#define DMA_HIFCR_CFEIF7_Pos (22U)
6466#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
6467#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6468#define DMA_HIFCR_CTCIF6_Pos (21U)
6469#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
6470#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6471#define DMA_HIFCR_CHTIF6_Pos (20U)
6472#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
6473#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6474#define DMA_HIFCR_CTEIF6_Pos (19U)
6475#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
6476#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6477#define DMA_HIFCR_CDMEIF6_Pos (18U)
6478#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
6479#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6480#define DMA_HIFCR_CFEIF6_Pos (16U)
6481#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
6482#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6483#define DMA_HIFCR_CTCIF5_Pos (11U)
6484#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
6485#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6486#define DMA_HIFCR_CHTIF5_Pos (10U)
6487#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
6488#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6489#define DMA_HIFCR_CTEIF5_Pos (9U)
6490#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
6491#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6492#define DMA_HIFCR_CDMEIF5_Pos (8U)
6493#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
6494#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6495#define DMA_HIFCR_CFEIF5_Pos (6U)
6496#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
6497#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6498#define DMA_HIFCR_CTCIF4_Pos (5U)
6499#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
6500#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6501#define DMA_HIFCR_CHTIF4_Pos (4U)
6502#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
6503#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6504#define DMA_HIFCR_CTEIF4_Pos (3U)
6505#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
6506#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6507#define DMA_HIFCR_CDMEIF4_Pos (2U)
6508#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
6509#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6510#define DMA_HIFCR_CFEIF4_Pos (0U)
6511#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
6512#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6513
6514/****************** Bit definition for DMA_SxPAR register ********************/
6515#define DMA_SxPAR_PA_Pos (0U)
6516#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
6517#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
6518
6519/****************** Bit definition for DMA_SxM0AR register ********************/
6520#define DMA_SxM0AR_M0A_Pos (0U)
6521#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
6522#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
6523
6524/****************** Bit definition for DMA_SxM1AR register ********************/
6525#define DMA_SxM1AR_M1A_Pos (0U)
6526#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
6527#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
6528
6529
6530/******************************************************************************/
6531/* */
6532/* AHB Master DMA2D Controller (DMA2D) */
6533/* */
6534/******************************************************************************/
6535
6536/******************** Bit definition for DMA2D_CR register ******************/
6537
6538#define DMA2D_CR_START_Pos (0U)
6539#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos)
6540#define DMA2D_CR_START DMA2D_CR_START_Msk
6541#define DMA2D_CR_SUSP_Pos (1U)
6542#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos)
6543#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk
6544#define DMA2D_CR_ABORT_Pos (2U)
6545#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos)
6546#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk
6547#define DMA2D_CR_TEIE_Pos (8U)
6548#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos)
6549#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk
6550#define DMA2D_CR_TCIE_Pos (9U)
6551#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos)
6552#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk
6553#define DMA2D_CR_TWIE_Pos (10U)
6554#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos)
6555#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk
6556#define DMA2D_CR_CAEIE_Pos (11U)
6557#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos)
6558#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk
6559#define DMA2D_CR_CTCIE_Pos (12U)
6560#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos)
6561#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk
6562#define DMA2D_CR_CEIE_Pos (13U)
6563#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos)
6564#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk
6565#define DMA2D_CR_MODE_Pos (16U)
6566#define DMA2D_CR_MODE_Msk (0x3UL << DMA2D_CR_MODE_Pos)
6567#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk
6568#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos)
6569#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos)
6570
6571/******************** Bit definition for DMA2D_ISR register *****************/
6572
6573#define DMA2D_ISR_TEIF_Pos (0U)
6574#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos)
6575#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk
6576#define DMA2D_ISR_TCIF_Pos (1U)
6577#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos)
6578#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk
6579#define DMA2D_ISR_TWIF_Pos (2U)
6580#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos)
6581#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk
6582#define DMA2D_ISR_CAEIF_Pos (3U)
6583#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos)
6584#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk
6585#define DMA2D_ISR_CTCIF_Pos (4U)
6586#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos)
6587#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk
6588#define DMA2D_ISR_CEIF_Pos (5U)
6589#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos)
6590#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk
6591
6592/******************** Bit definition for DMA2D_IFCR register ****************/
6593
6594#define DMA2D_IFCR_CTEIF_Pos (0U)
6595#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos)
6596#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk
6597#define DMA2D_IFCR_CTCIF_Pos (1U)
6598#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos)
6599#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk
6600#define DMA2D_IFCR_CTWIF_Pos (2U)
6601#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos)
6602#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk
6603#define DMA2D_IFCR_CAECIF_Pos (3U)
6604#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos)
6605#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk
6606#define DMA2D_IFCR_CCTCIF_Pos (4U)
6607#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos)
6608#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk
6609#define DMA2D_IFCR_CCEIF_Pos (5U)
6610#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos)
6611#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk
6612
6613/* Legacy defines */
6614#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF
6615#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF
6616#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF
6617#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF
6618#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF
6619#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF
6620
6621/******************** Bit definition for DMA2D_FGMAR register ***************/
6622
6623#define DMA2D_FGMAR_MA_Pos (0U)
6624#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)
6625#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk
6626
6627/******************** Bit definition for DMA2D_FGOR register ****************/
6628
6629#define DMA2D_FGOR_LO_Pos (0U)
6630#define DMA2D_FGOR_LO_Msk (0x3FFFUL << DMA2D_FGOR_LO_Pos)
6631#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk
6632
6633/******************** Bit definition for DMA2D_BGMAR register ***************/
6634
6635#define DMA2D_BGMAR_MA_Pos (0U)
6636#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)
6637#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk
6638
6639/******************** Bit definition for DMA2D_BGOR register ****************/
6640
6641#define DMA2D_BGOR_LO_Pos (0U)
6642#define DMA2D_BGOR_LO_Msk (0x3FFFUL << DMA2D_BGOR_LO_Pos)
6643#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk
6644
6645/******************** Bit definition for DMA2D_FGPFCCR register *************/
6646
6647#define DMA2D_FGPFCCR_CM_Pos (0U)
6648#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos)
6649#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk
6650#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos)
6651#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos)
6652#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos)
6653#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos)
6654#define DMA2D_FGPFCCR_CCM_Pos (4U)
6655#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos)
6656#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk
6657#define DMA2D_FGPFCCR_START_Pos (5U)
6658#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos)
6659#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk
6660#define DMA2D_FGPFCCR_CS_Pos (8U)
6661#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos)
6662#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk
6663#define DMA2D_FGPFCCR_AM_Pos (16U)
6664#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos)
6665#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk
6666#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos)
6667#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos)
6668#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
6669#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)
6670#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk
6671
6672/******************** Bit definition for DMA2D_FGCOLR register **************/
6673
6674#define DMA2D_FGCOLR_BLUE_Pos (0U)
6675#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)
6676#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk
6677#define DMA2D_FGCOLR_GREEN_Pos (8U)
6678#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)
6679#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk
6680#define DMA2D_FGCOLR_RED_Pos (16U)
6681#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos)
6682#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk
6683
6684/******************** Bit definition for DMA2D_BGPFCCR register *************/
6685
6686#define DMA2D_BGPFCCR_CM_Pos (0U)
6687#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos)
6688#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk
6689#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos)
6690#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos)
6691#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos)
6692#define DMA2D_BGPFCCR_CM_3 0x00000008U
6693#define DMA2D_BGPFCCR_CCM_Pos (4U)
6694#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos)
6695#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk
6696#define DMA2D_BGPFCCR_START_Pos (5U)
6697#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos)
6698#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk
6699#define DMA2D_BGPFCCR_CS_Pos (8U)
6700#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos)
6701#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk
6702#define DMA2D_BGPFCCR_AM_Pos (16U)
6703#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos)
6704#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk
6705#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos)
6706#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos)
6707#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
6708#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)
6709#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk
6710
6711/******************** Bit definition for DMA2D_BGCOLR register **************/
6712
6713#define DMA2D_BGCOLR_BLUE_Pos (0U)
6714#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)
6715#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk
6716#define DMA2D_BGCOLR_GREEN_Pos (8U)
6717#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)
6718#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk
6719#define DMA2D_BGCOLR_RED_Pos (16U)
6720#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos)
6721#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk
6722
6723/******************** Bit definition for DMA2D_FGCMAR register **************/
6724
6725#define DMA2D_FGCMAR_MA_Pos (0U)
6726#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)
6727#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk
6728
6729/******************** Bit definition for DMA2D_BGCMAR register **************/
6730
6731#define DMA2D_BGCMAR_MA_Pos (0U)
6732#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)
6733#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk
6734
6735/******************** Bit definition for DMA2D_OPFCCR register **************/
6736
6737#define DMA2D_OPFCCR_CM_Pos (0U)
6738#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos)
6739#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk
6740#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos)
6741#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos)
6742#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos)
6743
6744/******************** Bit definition for DMA2D_OCOLR register ***************/
6745
6747
6748#define DMA2D_OCOLR_BLUE_1 0x000000FFU
6749#define DMA2D_OCOLR_GREEN_1 0x0000FF00U
6750#define DMA2D_OCOLR_RED_1 0x00FF0000U
6751#define DMA2D_OCOLR_ALPHA_1 0xFF000000U
6752
6754#define DMA2D_OCOLR_BLUE_2 0x0000001FU
6755#define DMA2D_OCOLR_GREEN_2 0x000007E0U
6756#define DMA2D_OCOLR_RED_2 0x0000F800U
6757
6759#define DMA2D_OCOLR_BLUE_3 0x0000001FU
6760#define DMA2D_OCOLR_GREEN_3 0x000003E0U
6761#define DMA2D_OCOLR_RED_3 0x00007C00U
6762#define DMA2D_OCOLR_ALPHA_3 0x00008000U
6763
6765#define DMA2D_OCOLR_BLUE_4 0x0000000FU
6766#define DMA2D_OCOLR_GREEN_4 0x000000F0U
6767#define DMA2D_OCOLR_RED_4 0x00000F00U
6768#define DMA2D_OCOLR_ALPHA_4 0x0000F000U
6769
6770/******************** Bit definition for DMA2D_OMAR register ****************/
6771
6772#define DMA2D_OMAR_MA_Pos (0U)
6773#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)
6774#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk
6775
6776/******************** Bit definition for DMA2D_OOR register *****************/
6777
6778#define DMA2D_OOR_LO_Pos (0U)
6779#define DMA2D_OOR_LO_Msk (0x3FFFUL << DMA2D_OOR_LO_Pos)
6780#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk
6781
6782/******************** Bit definition for DMA2D_NLR register *****************/
6783
6784#define DMA2D_NLR_NL_Pos (0U)
6785#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos)
6786#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk
6787#define DMA2D_NLR_PL_Pos (16U)
6788#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos)
6789#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk
6790
6791/******************** Bit definition for DMA2D_LWR register *****************/
6792
6793#define DMA2D_LWR_LW_Pos (0U)
6794#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos)
6795#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk
6796
6797/******************** Bit definition for DMA2D_AMTCR register ***************/
6798
6799#define DMA2D_AMTCR_EN_Pos (0U)
6800#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos)
6801#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk
6802#define DMA2D_AMTCR_DT_Pos (8U)
6803#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos)
6804#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk
6805
6806/******************** Bit definition for DMA2D_FGCLUT register **************/
6807
6808/******************** Bit definition for DMA2D_BGCLUT register **************/
6809
6810
6811/******************************************************************************/
6812/* */
6813/* External Interrupt/Event Controller */
6814/* */
6815/******************************************************************************/
6816/******************* Bit definition for EXTI_IMR register *******************/
6817#define EXTI_IMR_MR0_Pos (0U)
6818#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
6819#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
6820#define EXTI_IMR_MR1_Pos (1U)
6821#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
6822#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
6823#define EXTI_IMR_MR2_Pos (2U)
6824#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
6825#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
6826#define EXTI_IMR_MR3_Pos (3U)
6827#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
6828#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
6829#define EXTI_IMR_MR4_Pos (4U)
6830#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
6831#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
6832#define EXTI_IMR_MR5_Pos (5U)
6833#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
6834#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
6835#define EXTI_IMR_MR6_Pos (6U)
6836#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
6837#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
6838#define EXTI_IMR_MR7_Pos (7U)
6839#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
6840#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
6841#define EXTI_IMR_MR8_Pos (8U)
6842#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
6843#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
6844#define EXTI_IMR_MR9_Pos (9U)
6845#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
6846#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
6847#define EXTI_IMR_MR10_Pos (10U)
6848#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
6849#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
6850#define EXTI_IMR_MR11_Pos (11U)
6851#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
6852#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
6853#define EXTI_IMR_MR12_Pos (12U)
6854#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
6855#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
6856#define EXTI_IMR_MR13_Pos (13U)
6857#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
6858#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
6859#define EXTI_IMR_MR14_Pos (14U)
6860#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
6861#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
6862#define EXTI_IMR_MR15_Pos (15U)
6863#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
6864#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
6865#define EXTI_IMR_MR16_Pos (16U)
6866#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
6867#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
6868#define EXTI_IMR_MR17_Pos (17U)
6869#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
6870#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
6871#define EXTI_IMR_MR18_Pos (18U)
6872#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
6873#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
6874#define EXTI_IMR_MR19_Pos (19U)
6875#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
6876#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
6877#define EXTI_IMR_MR20_Pos (20U)
6878#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
6879#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
6880#define EXTI_IMR_MR21_Pos (21U)
6881#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
6882#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
6883#define EXTI_IMR_MR22_Pos (22U)
6884#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
6885#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
6886
6887/* Reference Defines */
6888#define EXTI_IMR_IM0 EXTI_IMR_MR0
6889#define EXTI_IMR_IM1 EXTI_IMR_MR1
6890#define EXTI_IMR_IM2 EXTI_IMR_MR2
6891#define EXTI_IMR_IM3 EXTI_IMR_MR3
6892#define EXTI_IMR_IM4 EXTI_IMR_MR4
6893#define EXTI_IMR_IM5 EXTI_IMR_MR5
6894#define EXTI_IMR_IM6 EXTI_IMR_MR6
6895#define EXTI_IMR_IM7 EXTI_IMR_MR7
6896#define EXTI_IMR_IM8 EXTI_IMR_MR8
6897#define EXTI_IMR_IM9 EXTI_IMR_MR9
6898#define EXTI_IMR_IM10 EXTI_IMR_MR10
6899#define EXTI_IMR_IM11 EXTI_IMR_MR11
6900#define EXTI_IMR_IM12 EXTI_IMR_MR12
6901#define EXTI_IMR_IM13 EXTI_IMR_MR13
6902#define EXTI_IMR_IM14 EXTI_IMR_MR14
6903#define EXTI_IMR_IM15 EXTI_IMR_MR15
6904#define EXTI_IMR_IM16 EXTI_IMR_MR16
6905#define EXTI_IMR_IM17 EXTI_IMR_MR17
6906#define EXTI_IMR_IM18 EXTI_IMR_MR18
6907#define EXTI_IMR_IM19 EXTI_IMR_MR19
6908#define EXTI_IMR_IM20 EXTI_IMR_MR20
6909#define EXTI_IMR_IM21 EXTI_IMR_MR21
6910#define EXTI_IMR_IM22 EXTI_IMR_MR22
6911#define EXTI_IMR_IM_Pos (0U)
6912#define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos)
6913#define EXTI_IMR_IM EXTI_IMR_IM_Msk
6914
6915/******************* Bit definition for EXTI_EMR register *******************/
6916#define EXTI_EMR_MR0_Pos (0U)
6917#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
6918#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
6919#define EXTI_EMR_MR1_Pos (1U)
6920#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
6921#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
6922#define EXTI_EMR_MR2_Pos (2U)
6923#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
6924#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
6925#define EXTI_EMR_MR3_Pos (3U)
6926#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
6927#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
6928#define EXTI_EMR_MR4_Pos (4U)
6929#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
6930#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
6931#define EXTI_EMR_MR5_Pos (5U)
6932#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
6933#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
6934#define EXTI_EMR_MR6_Pos (6U)
6935#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
6936#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
6937#define EXTI_EMR_MR7_Pos (7U)
6938#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
6939#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
6940#define EXTI_EMR_MR8_Pos (8U)
6941#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
6942#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
6943#define EXTI_EMR_MR9_Pos (9U)
6944#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
6945#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
6946#define EXTI_EMR_MR10_Pos (10U)
6947#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
6948#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
6949#define EXTI_EMR_MR11_Pos (11U)
6950#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
6951#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
6952#define EXTI_EMR_MR12_Pos (12U)
6953#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
6954#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
6955#define EXTI_EMR_MR13_Pos (13U)
6956#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
6957#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
6958#define EXTI_EMR_MR14_Pos (14U)
6959#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
6960#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
6961#define EXTI_EMR_MR15_Pos (15U)
6962#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
6963#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
6964#define EXTI_EMR_MR16_Pos (16U)
6965#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
6966#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
6967#define EXTI_EMR_MR17_Pos (17U)
6968#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
6969#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
6970#define EXTI_EMR_MR18_Pos (18U)
6971#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
6972#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
6973#define EXTI_EMR_MR19_Pos (19U)
6974#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
6975#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
6976#define EXTI_EMR_MR20_Pos (20U)
6977#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
6978#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
6979#define EXTI_EMR_MR21_Pos (21U)
6980#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
6981#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
6982#define EXTI_EMR_MR22_Pos (22U)
6983#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
6984#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
6985
6986/* Reference Defines */
6987#define EXTI_EMR_EM0 EXTI_EMR_MR0
6988#define EXTI_EMR_EM1 EXTI_EMR_MR1
6989#define EXTI_EMR_EM2 EXTI_EMR_MR2
6990#define EXTI_EMR_EM3 EXTI_EMR_MR3
6991#define EXTI_EMR_EM4 EXTI_EMR_MR4
6992#define EXTI_EMR_EM5 EXTI_EMR_MR5
6993#define EXTI_EMR_EM6 EXTI_EMR_MR6
6994#define EXTI_EMR_EM7 EXTI_EMR_MR7
6995#define EXTI_EMR_EM8 EXTI_EMR_MR8
6996#define EXTI_EMR_EM9 EXTI_EMR_MR9
6997#define EXTI_EMR_EM10 EXTI_EMR_MR10
6998#define EXTI_EMR_EM11 EXTI_EMR_MR11
6999#define EXTI_EMR_EM12 EXTI_EMR_MR12
7000#define EXTI_EMR_EM13 EXTI_EMR_MR13
7001#define EXTI_EMR_EM14 EXTI_EMR_MR14
7002#define EXTI_EMR_EM15 EXTI_EMR_MR15
7003#define EXTI_EMR_EM16 EXTI_EMR_MR16
7004#define EXTI_EMR_EM17 EXTI_EMR_MR17
7005#define EXTI_EMR_EM18 EXTI_EMR_MR18
7006#define EXTI_EMR_EM19 EXTI_EMR_MR19
7007#define EXTI_EMR_EM20 EXTI_EMR_MR20
7008#define EXTI_EMR_EM21 EXTI_EMR_MR21
7009#define EXTI_EMR_EM22 EXTI_EMR_MR22
7010
7011/****************** Bit definition for EXTI_RTSR register *******************/
7012#define EXTI_RTSR_TR0_Pos (0U)
7013#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
7014#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
7015#define EXTI_RTSR_TR1_Pos (1U)
7016#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
7017#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
7018#define EXTI_RTSR_TR2_Pos (2U)
7019#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
7020#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
7021#define EXTI_RTSR_TR3_Pos (3U)
7022#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
7023#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
7024#define EXTI_RTSR_TR4_Pos (4U)
7025#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
7026#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
7027#define EXTI_RTSR_TR5_Pos (5U)
7028#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
7029#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
7030#define EXTI_RTSR_TR6_Pos (6U)
7031#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
7032#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
7033#define EXTI_RTSR_TR7_Pos (7U)
7034#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
7035#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
7036#define EXTI_RTSR_TR8_Pos (8U)
7037#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
7038#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
7039#define EXTI_RTSR_TR9_Pos (9U)
7040#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
7041#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
7042#define EXTI_RTSR_TR10_Pos (10U)
7043#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
7044#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
7045#define EXTI_RTSR_TR11_Pos (11U)
7046#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
7047#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
7048#define EXTI_RTSR_TR12_Pos (12U)
7049#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
7050#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
7051#define EXTI_RTSR_TR13_Pos (13U)
7052#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
7053#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
7054#define EXTI_RTSR_TR14_Pos (14U)
7055#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
7056#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
7057#define EXTI_RTSR_TR15_Pos (15U)
7058#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
7059#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
7060#define EXTI_RTSR_TR16_Pos (16U)
7061#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
7062#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
7063#define EXTI_RTSR_TR17_Pos (17U)
7064#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
7065#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
7066#define EXTI_RTSR_TR18_Pos (18U)
7067#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
7068#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
7069#define EXTI_RTSR_TR19_Pos (19U)
7070#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
7071#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
7072#define EXTI_RTSR_TR20_Pos (20U)
7073#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
7074#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
7075#define EXTI_RTSR_TR21_Pos (21U)
7076#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
7077#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
7078#define EXTI_RTSR_TR22_Pos (22U)
7079#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
7080#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
7081
7082/****************** Bit definition for EXTI_FTSR register *******************/
7083#define EXTI_FTSR_TR0_Pos (0U)
7084#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
7085#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
7086#define EXTI_FTSR_TR1_Pos (1U)
7087#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
7088#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
7089#define EXTI_FTSR_TR2_Pos (2U)
7090#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
7091#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
7092#define EXTI_FTSR_TR3_Pos (3U)
7093#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
7094#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
7095#define EXTI_FTSR_TR4_Pos (4U)
7096#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
7097#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
7098#define EXTI_FTSR_TR5_Pos (5U)
7099#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
7100#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
7101#define EXTI_FTSR_TR6_Pos (6U)
7102#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
7103#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
7104#define EXTI_FTSR_TR7_Pos (7U)
7105#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
7106#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
7107#define EXTI_FTSR_TR8_Pos (8U)
7108#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
7109#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
7110#define EXTI_FTSR_TR9_Pos (9U)
7111#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
7112#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
7113#define EXTI_FTSR_TR10_Pos (10U)
7114#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
7115#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
7116#define EXTI_FTSR_TR11_Pos (11U)
7117#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
7118#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
7119#define EXTI_FTSR_TR12_Pos (12U)
7120#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
7121#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
7122#define EXTI_FTSR_TR13_Pos (13U)
7123#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
7124#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
7125#define EXTI_FTSR_TR14_Pos (14U)
7126#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
7127#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
7128#define EXTI_FTSR_TR15_Pos (15U)
7129#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
7130#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
7131#define EXTI_FTSR_TR16_Pos (16U)
7132#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
7133#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
7134#define EXTI_FTSR_TR17_Pos (17U)
7135#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
7136#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
7137#define EXTI_FTSR_TR18_Pos (18U)
7138#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
7139#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
7140#define EXTI_FTSR_TR19_Pos (19U)
7141#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
7142#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
7143#define EXTI_FTSR_TR20_Pos (20U)
7144#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
7145#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
7146#define EXTI_FTSR_TR21_Pos (21U)
7147#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
7148#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
7149#define EXTI_FTSR_TR22_Pos (22U)
7150#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
7151#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
7152
7153/****************** Bit definition for EXTI_SWIER register ******************/
7154#define EXTI_SWIER_SWIER0_Pos (0U)
7155#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
7156#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
7157#define EXTI_SWIER_SWIER1_Pos (1U)
7158#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
7159#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
7160#define EXTI_SWIER_SWIER2_Pos (2U)
7161#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
7162#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
7163#define EXTI_SWIER_SWIER3_Pos (3U)
7164#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
7165#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
7166#define EXTI_SWIER_SWIER4_Pos (4U)
7167#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
7168#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
7169#define EXTI_SWIER_SWIER5_Pos (5U)
7170#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
7171#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
7172#define EXTI_SWIER_SWIER6_Pos (6U)
7173#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
7174#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
7175#define EXTI_SWIER_SWIER7_Pos (7U)
7176#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
7177#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
7178#define EXTI_SWIER_SWIER8_Pos (8U)
7179#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
7180#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
7181#define EXTI_SWIER_SWIER9_Pos (9U)
7182#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
7183#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
7184#define EXTI_SWIER_SWIER10_Pos (10U)
7185#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
7186#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
7187#define EXTI_SWIER_SWIER11_Pos (11U)
7188#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
7189#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
7190#define EXTI_SWIER_SWIER12_Pos (12U)
7191#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
7192#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
7193#define EXTI_SWIER_SWIER13_Pos (13U)
7194#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
7195#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
7196#define EXTI_SWIER_SWIER14_Pos (14U)
7197#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
7198#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
7199#define EXTI_SWIER_SWIER15_Pos (15U)
7200#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
7201#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
7202#define EXTI_SWIER_SWIER16_Pos (16U)
7203#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
7204#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
7205#define EXTI_SWIER_SWIER17_Pos (17U)
7206#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
7207#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
7208#define EXTI_SWIER_SWIER18_Pos (18U)
7209#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
7210#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
7211#define EXTI_SWIER_SWIER19_Pos (19U)
7212#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
7213#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
7214#define EXTI_SWIER_SWIER20_Pos (20U)
7215#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
7216#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
7217#define EXTI_SWIER_SWIER21_Pos (21U)
7218#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
7219#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
7220#define EXTI_SWIER_SWIER22_Pos (22U)
7221#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
7222#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
7223
7224/******************* Bit definition for EXTI_PR register ********************/
7225#define EXTI_PR_PR0_Pos (0U)
7226#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
7227#define EXTI_PR_PR0 EXTI_PR_PR0_Msk
7228#define EXTI_PR_PR1_Pos (1U)
7229#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
7230#define EXTI_PR_PR1 EXTI_PR_PR1_Msk
7231#define EXTI_PR_PR2_Pos (2U)
7232#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
7233#define EXTI_PR_PR2 EXTI_PR_PR2_Msk
7234#define EXTI_PR_PR3_Pos (3U)
7235#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
7236#define EXTI_PR_PR3 EXTI_PR_PR3_Msk
7237#define EXTI_PR_PR4_Pos (4U)
7238#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
7239#define EXTI_PR_PR4 EXTI_PR_PR4_Msk
7240#define EXTI_PR_PR5_Pos (5U)
7241#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
7242#define EXTI_PR_PR5 EXTI_PR_PR5_Msk
7243#define EXTI_PR_PR6_Pos (6U)
7244#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
7245#define EXTI_PR_PR6 EXTI_PR_PR6_Msk
7246#define EXTI_PR_PR7_Pos (7U)
7247#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
7248#define EXTI_PR_PR7 EXTI_PR_PR7_Msk
7249#define EXTI_PR_PR8_Pos (8U)
7250#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
7251#define EXTI_PR_PR8 EXTI_PR_PR8_Msk
7252#define EXTI_PR_PR9_Pos (9U)
7253#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
7254#define EXTI_PR_PR9 EXTI_PR_PR9_Msk
7255#define EXTI_PR_PR10_Pos (10U)
7256#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
7257#define EXTI_PR_PR10 EXTI_PR_PR10_Msk
7258#define EXTI_PR_PR11_Pos (11U)
7259#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
7260#define EXTI_PR_PR11 EXTI_PR_PR11_Msk
7261#define EXTI_PR_PR12_Pos (12U)
7262#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
7263#define EXTI_PR_PR12 EXTI_PR_PR12_Msk
7264#define EXTI_PR_PR13_Pos (13U)
7265#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
7266#define EXTI_PR_PR13 EXTI_PR_PR13_Msk
7267#define EXTI_PR_PR14_Pos (14U)
7268#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
7269#define EXTI_PR_PR14 EXTI_PR_PR14_Msk
7270#define EXTI_PR_PR15_Pos (15U)
7271#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
7272#define EXTI_PR_PR15 EXTI_PR_PR15_Msk
7273#define EXTI_PR_PR16_Pos (16U)
7274#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
7275#define EXTI_PR_PR16 EXTI_PR_PR16_Msk
7276#define EXTI_PR_PR17_Pos (17U)
7277#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
7278#define EXTI_PR_PR17 EXTI_PR_PR17_Msk
7279#define EXTI_PR_PR18_Pos (18U)
7280#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
7281#define EXTI_PR_PR18 EXTI_PR_PR18_Msk
7282#define EXTI_PR_PR19_Pos (19U)
7283#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
7284#define EXTI_PR_PR19 EXTI_PR_PR19_Msk
7285#define EXTI_PR_PR20_Pos (20U)
7286#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
7287#define EXTI_PR_PR20 EXTI_PR_PR20_Msk
7288#define EXTI_PR_PR21_Pos (21U)
7289#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
7290#define EXTI_PR_PR21 EXTI_PR_PR21_Msk
7291#define EXTI_PR_PR22_Pos (22U)
7292#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
7293#define EXTI_PR_PR22 EXTI_PR_PR22_Msk
7294
7295/******************************************************************************/
7296/* */
7297/* FLASH */
7298/* */
7299/******************************************************************************/
7300/******************* Bits definition for FLASH_ACR register *****************/
7301#define FLASH_ACR_LATENCY_Pos (0U)
7302#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)
7303#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
7304#define FLASH_ACR_LATENCY_0WS 0x00000000U
7305#define FLASH_ACR_LATENCY_1WS 0x00000001U
7306#define FLASH_ACR_LATENCY_2WS 0x00000002U
7307#define FLASH_ACR_LATENCY_3WS 0x00000003U
7308#define FLASH_ACR_LATENCY_4WS 0x00000004U
7309#define FLASH_ACR_LATENCY_5WS 0x00000005U
7310#define FLASH_ACR_LATENCY_6WS 0x00000006U
7311#define FLASH_ACR_LATENCY_7WS 0x00000007U
7312
7313#define FLASH_ACR_LATENCY_8WS 0x00000008U
7314#define FLASH_ACR_LATENCY_9WS 0x00000009U
7315#define FLASH_ACR_LATENCY_10WS 0x0000000AU
7316#define FLASH_ACR_LATENCY_11WS 0x0000000BU
7317#define FLASH_ACR_LATENCY_12WS 0x0000000CU
7318#define FLASH_ACR_LATENCY_13WS 0x0000000DU
7319#define FLASH_ACR_LATENCY_14WS 0x0000000EU
7320#define FLASH_ACR_LATENCY_15WS 0x0000000FU
7321
7322#define FLASH_ACR_PRFTEN_Pos (8U)
7323#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
7324#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
7325#define FLASH_ACR_ICEN_Pos (9U)
7326#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
7327#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
7328#define FLASH_ACR_DCEN_Pos (10U)
7329#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
7330#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
7331#define FLASH_ACR_ICRST_Pos (11U)
7332#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
7333#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
7334#define FLASH_ACR_DCRST_Pos (12U)
7335#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
7336#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
7337
7338/******************* Bits definition for FLASH_SR register ******************/
7339#define FLASH_SR_EOP_Pos (0U)
7340#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
7341#define FLASH_SR_EOP FLASH_SR_EOP_Msk
7342#define FLASH_SR_OPERR_Pos (1U)
7343#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
7344#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
7345#define FLASH_SR_WRPERR_Pos (4U)
7346#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
7347#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
7348#define FLASH_SR_PGAERR_Pos (5U)
7349#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
7350#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
7351#define FLASH_SR_PGPERR_Pos (6U)
7352#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)
7353#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
7354#define FLASH_SR_PGSERR_Pos (7U)
7355#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
7356#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
7357#define FLASH_SR_RDERR_Pos (8U)
7358#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)
7359#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
7360#define FLASH_SR_BSY_Pos (16U)
7361#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
7362#define FLASH_SR_BSY FLASH_SR_BSY_Msk
7363
7364/******************* Bits definition for FLASH_CR register ******************/
7365#define FLASH_CR_PG_Pos (0U)
7366#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
7367#define FLASH_CR_PG FLASH_CR_PG_Msk
7368#define FLASH_CR_SER_Pos (1U)
7369#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
7370#define FLASH_CR_SER FLASH_CR_SER_Msk
7371#define FLASH_CR_MER_Pos (2U)
7372#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
7373#define FLASH_CR_MER FLASH_CR_MER_Msk
7374#define FLASH_CR_MER1 FLASH_CR_MER
7375#define FLASH_CR_SNB_Pos (3U)
7376#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos)
7377#define FLASH_CR_SNB FLASH_CR_SNB_Msk
7378#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos)
7379#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos)
7380#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos)
7381#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos)
7382#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos)
7383#define FLASH_CR_PSIZE_Pos (8U)
7384#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
7385#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
7386#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
7387#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
7388#define FLASH_CR_MER2_Pos (15U)
7389#define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos)
7390#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
7391#define FLASH_CR_STRT_Pos (16U)
7392#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
7393#define FLASH_CR_STRT FLASH_CR_STRT_Msk
7394#define FLASH_CR_EOPIE_Pos (24U)
7395#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
7396#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
7397#define FLASH_CR_ERRIE_Pos (25U)
7398#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
7399#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
7400#define FLASH_CR_LOCK_Pos (31U)
7401#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
7402#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
7403
7404/******************* Bits definition for FLASH_OPTCR register ***************/
7405#define FLASH_OPTCR_OPTLOCK_Pos (0U)
7406#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
7407#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
7408#define FLASH_OPTCR_OPTSTRT_Pos (1U)
7409#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
7410#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
7411
7412#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
7413#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
7414#define FLASH_OPTCR_BOR_LEV_Pos (2U)
7415#define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
7416#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
7417#define FLASH_OPTCR_BFB2_Pos (4U)
7418#define FLASH_OPTCR_BFB2_Msk (0x1UL << FLASH_OPTCR_BFB2_Pos)
7419#define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
7420#define FLASH_OPTCR_WDG_SW_Pos (5U)
7421#define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos)
7422#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
7423#define FLASH_OPTCR_nRST_STOP_Pos (6U)
7424#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
7425#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
7426#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
7427#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
7428#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
7429#define FLASH_OPTCR_RDP_Pos (8U)
7430#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)
7431#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
7432#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)
7433#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)
7434#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)
7435#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)
7436#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)
7437#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)
7438#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)
7439#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)
7440#define FLASH_OPTCR_nWRP_Pos (16U)
7441#define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos)
7442#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
7443#define FLASH_OPTCR_nWRP_0 0x00010000U
7444#define FLASH_OPTCR_nWRP_1 0x00020000U
7445#define FLASH_OPTCR_nWRP_2 0x00040000U
7446#define FLASH_OPTCR_nWRP_3 0x00080000U
7447#define FLASH_OPTCR_nWRP_4 0x00100000U
7448#define FLASH_OPTCR_nWRP_5 0x00200000U
7449#define FLASH_OPTCR_nWRP_6 0x00400000U
7450#define FLASH_OPTCR_nWRP_7 0x00800000U
7451#define FLASH_OPTCR_nWRP_8 0x01000000U
7452#define FLASH_OPTCR_nWRP_9 0x02000000U
7453#define FLASH_OPTCR_nWRP_10 0x04000000U
7454#define FLASH_OPTCR_nWRP_11 0x08000000U
7455#define FLASH_OPTCR_DB1M_Pos (30U)
7456#define FLASH_OPTCR_DB1M_Msk (0x1UL << FLASH_OPTCR_DB1M_Pos)
7457#define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
7458#define FLASH_OPTCR_SPRMOD_Pos (31U)
7459#define FLASH_OPTCR_SPRMOD_Msk (0x1UL << FLASH_OPTCR_SPRMOD_Pos)
7460#define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
7461
7462/****************** Bits definition for FLASH_OPTCR1 register ***************/
7463#define FLASH_OPTCR1_nWRP_Pos (16U)
7464#define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)
7465#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
7466#define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos)
7467#define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos)
7468#define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos)
7469#define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos)
7470#define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos)
7471#define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos)
7472#define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos)
7473#define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos)
7474#define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos)
7475#define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos)
7476#define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos)
7477#define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos)
7478/* Legacy defines */
7479#define FLASH_SR_SOP_Pos FLASH_SR_OPERR_Pos
7480#define FLASH_SR_SOP_Msk FLASH_SR_OPERR_Msk
7481#define FLASH_SR_SOP FLASH_SR_OPERR
7482#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
7483#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)
7484#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
7485#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
7486#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)
7487#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
7488
7489/******************************************************************************/
7490/* */
7491/* Flexible Memory Controller */
7492/* */
7493/******************************************************************************/
7494/****************** Bit definition for FMC_BCR1 register *******************/
7495#define FMC_BCR1_MBKEN_Pos (0U)
7496#define FMC_BCR1_MBKEN_Msk (0x1UL << FMC_BCR1_MBKEN_Pos)
7497#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk
7498#define FMC_BCR1_MUXEN_Pos (1U)
7499#define FMC_BCR1_MUXEN_Msk (0x1UL << FMC_BCR1_MUXEN_Pos)
7500#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk
7501
7502#define FMC_BCR1_MTYP_Pos (2U)
7503#define FMC_BCR1_MTYP_Msk (0x3UL << FMC_BCR1_MTYP_Pos)
7504#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk
7505#define FMC_BCR1_MTYP_0 (0x1UL << FMC_BCR1_MTYP_Pos)
7506#define FMC_BCR1_MTYP_1 (0x2UL << FMC_BCR1_MTYP_Pos)
7507
7508#define FMC_BCR1_MWID_Pos (4U)
7509#define FMC_BCR1_MWID_Msk (0x3UL << FMC_BCR1_MWID_Pos)
7510#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk
7511#define FMC_BCR1_MWID_0 (0x1UL << FMC_BCR1_MWID_Pos)
7512#define FMC_BCR1_MWID_1 (0x2UL << FMC_BCR1_MWID_Pos)
7513
7514#define FMC_BCR1_FACCEN_Pos (6U)
7515#define FMC_BCR1_FACCEN_Msk (0x1UL << FMC_BCR1_FACCEN_Pos)
7516#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk
7517#define FMC_BCR1_BURSTEN_Pos (8U)
7518#define FMC_BCR1_BURSTEN_Msk (0x1UL << FMC_BCR1_BURSTEN_Pos)
7519#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk
7520#define FMC_BCR1_WAITPOL_Pos (9U)
7521#define FMC_BCR1_WAITPOL_Msk (0x1UL << FMC_BCR1_WAITPOL_Pos)
7522#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk
7523#define FMC_BCR1_WRAPMOD_Pos (10U)
7524#define FMC_BCR1_WRAPMOD_Msk (0x1UL << FMC_BCR1_WRAPMOD_Pos)
7525#define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk
7526#define FMC_BCR1_WAITCFG_Pos (11U)
7527#define FMC_BCR1_WAITCFG_Msk (0x1UL << FMC_BCR1_WAITCFG_Pos)
7528#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk
7529#define FMC_BCR1_WREN_Pos (12U)
7530#define FMC_BCR1_WREN_Msk (0x1UL << FMC_BCR1_WREN_Pos)
7531#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk
7532#define FMC_BCR1_WAITEN_Pos (13U)
7533#define FMC_BCR1_WAITEN_Msk (0x1UL << FMC_BCR1_WAITEN_Pos)
7534#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk
7535#define FMC_BCR1_EXTMOD_Pos (14U)
7536#define FMC_BCR1_EXTMOD_Msk (0x1UL << FMC_BCR1_EXTMOD_Pos)
7537#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk
7538#define FMC_BCR1_ASYNCWAIT_Pos (15U)
7539#define FMC_BCR1_ASYNCWAIT_Msk (0x1UL << FMC_BCR1_ASYNCWAIT_Pos)
7540#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk
7541#define FMC_BCR1_CPSIZE_Pos (16U)
7542#define FMC_BCR1_CPSIZE_Msk (0x7UL << FMC_BCR1_CPSIZE_Pos)
7543#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk
7544#define FMC_BCR1_CPSIZE_0 (0x1UL << FMC_BCR1_CPSIZE_Pos)
7545#define FMC_BCR1_CPSIZE_1 (0x2UL << FMC_BCR1_CPSIZE_Pos)
7546#define FMC_BCR1_CPSIZE_2 (0x4UL << FMC_BCR1_CPSIZE_Pos)
7547#define FMC_BCR1_CBURSTRW_Pos (19U)
7548#define FMC_BCR1_CBURSTRW_Msk (0x1UL << FMC_BCR1_CBURSTRW_Pos)
7549#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk
7550#define FMC_BCR1_CCLKEN_Pos (20U)
7551#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
7552#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
7553
7554/****************** Bit definition for FMC_BCR2 register *******************/
7555#define FMC_BCR2_MBKEN_Pos (0U)
7556#define FMC_BCR2_MBKEN_Msk (0x1UL << FMC_BCR2_MBKEN_Pos)
7557#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk
7558#define FMC_BCR2_MUXEN_Pos (1U)
7559#define FMC_BCR2_MUXEN_Msk (0x1UL << FMC_BCR2_MUXEN_Pos)
7560#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk
7561
7562#define FMC_BCR2_MTYP_Pos (2U)
7563#define FMC_BCR2_MTYP_Msk (0x3UL << FMC_BCR2_MTYP_Pos)
7564#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk
7565#define FMC_BCR2_MTYP_0 (0x1UL << FMC_BCR2_MTYP_Pos)
7566#define FMC_BCR2_MTYP_1 (0x2UL << FMC_BCR2_MTYP_Pos)
7567
7568#define FMC_BCR2_MWID_Pos (4U)
7569#define FMC_BCR2_MWID_Msk (0x3UL << FMC_BCR2_MWID_Pos)
7570#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk
7571#define FMC_BCR2_MWID_0 (0x1UL << FMC_BCR2_MWID_Pos)
7572#define FMC_BCR2_MWID_1 (0x2UL << FMC_BCR2_MWID_Pos)
7573
7574#define FMC_BCR2_FACCEN_Pos (6U)
7575#define FMC_BCR2_FACCEN_Msk (0x1UL << FMC_BCR2_FACCEN_Pos)
7576#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk
7577#define FMC_BCR2_BURSTEN_Pos (8U)
7578#define FMC_BCR2_BURSTEN_Msk (0x1UL << FMC_BCR2_BURSTEN_Pos)
7579#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk
7580#define FMC_BCR2_WAITPOL_Pos (9U)
7581#define FMC_BCR2_WAITPOL_Msk (0x1UL << FMC_BCR2_WAITPOL_Pos)
7582#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk
7583#define FMC_BCR2_WRAPMOD_Pos (10U)
7584#define FMC_BCR2_WRAPMOD_Msk (0x1UL << FMC_BCR2_WRAPMOD_Pos)
7585#define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk
7586#define FMC_BCR2_WAITCFG_Pos (11U)
7587#define FMC_BCR2_WAITCFG_Msk (0x1UL << FMC_BCR2_WAITCFG_Pos)
7588#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk
7589#define FMC_BCR2_WREN_Pos (12U)
7590#define FMC_BCR2_WREN_Msk (0x1UL << FMC_BCR2_WREN_Pos)
7591#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk
7592#define FMC_BCR2_WAITEN_Pos (13U)
7593#define FMC_BCR2_WAITEN_Msk (0x1UL << FMC_BCR2_WAITEN_Pos)
7594#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk
7595#define FMC_BCR2_EXTMOD_Pos (14U)
7596#define FMC_BCR2_EXTMOD_Msk (0x1UL << FMC_BCR2_EXTMOD_Pos)
7597#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk
7598#define FMC_BCR2_ASYNCWAIT_Pos (15U)
7599#define FMC_BCR2_ASYNCWAIT_Msk (0x1UL << FMC_BCR2_ASYNCWAIT_Pos)
7600#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk
7601#define FMC_BCR2_CPSIZE_Pos (16U)
7602#define FMC_BCR2_CPSIZE_Msk (0x7UL << FMC_BCR2_CPSIZE_Pos)
7603#define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk
7604#define FMC_BCR2_CPSIZE_0 (0x1UL << FMC_BCR2_CPSIZE_Pos)
7605#define FMC_BCR2_CPSIZE_1 (0x2UL << FMC_BCR2_CPSIZE_Pos)
7606#define FMC_BCR2_CPSIZE_2 (0x4UL << FMC_BCR2_CPSIZE_Pos)
7607#define FMC_BCR2_CBURSTRW_Pos (19U)
7608#define FMC_BCR2_CBURSTRW_Msk (0x1UL << FMC_BCR2_CBURSTRW_Pos)
7609#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk
7610
7611/****************** Bit definition for FMC_BCR3 register *******************/
7612#define FMC_BCR3_MBKEN_Pos (0U)
7613#define FMC_BCR3_MBKEN_Msk (0x1UL << FMC_BCR3_MBKEN_Pos)
7614#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk
7615#define FMC_BCR3_MUXEN_Pos (1U)
7616#define FMC_BCR3_MUXEN_Msk (0x1UL << FMC_BCR3_MUXEN_Pos)
7617#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk
7618
7619#define FMC_BCR3_MTYP_Pos (2U)
7620#define FMC_BCR3_MTYP_Msk (0x3UL << FMC_BCR3_MTYP_Pos)
7621#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk
7622#define FMC_BCR3_MTYP_0 (0x1UL << FMC_BCR3_MTYP_Pos)
7623#define FMC_BCR3_MTYP_1 (0x2UL << FMC_BCR3_MTYP_Pos)
7624
7625#define FMC_BCR3_MWID_Pos (4U)
7626#define FMC_BCR3_MWID_Msk (0x3UL << FMC_BCR3_MWID_Pos)
7627#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk
7628#define FMC_BCR3_MWID_0 (0x1UL << FMC_BCR3_MWID_Pos)
7629#define FMC_BCR3_MWID_1 (0x2UL << FMC_BCR3_MWID_Pos)
7630
7631#define FMC_BCR3_FACCEN_Pos (6U)
7632#define FMC_BCR3_FACCEN_Msk (0x1UL << FMC_BCR3_FACCEN_Pos)
7633#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk
7634#define FMC_BCR3_BURSTEN_Pos (8U)
7635#define FMC_BCR3_BURSTEN_Msk (0x1UL << FMC_BCR3_BURSTEN_Pos)
7636#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk
7637#define FMC_BCR3_WAITPOL_Pos (9U)
7638#define FMC_BCR3_WAITPOL_Msk (0x1UL << FMC_BCR3_WAITPOL_Pos)
7639#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk
7640#define FMC_BCR3_WRAPMOD_Pos (10U)
7641#define FMC_BCR3_WRAPMOD_Msk (0x1UL << FMC_BCR3_WRAPMOD_Pos)
7642#define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk
7643#define FMC_BCR3_WAITCFG_Pos (11U)
7644#define FMC_BCR3_WAITCFG_Msk (0x1UL << FMC_BCR3_WAITCFG_Pos)
7645#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk
7646#define FMC_BCR3_WREN_Pos (12U)
7647#define FMC_BCR3_WREN_Msk (0x1UL << FMC_BCR3_WREN_Pos)
7648#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk
7649#define FMC_BCR3_WAITEN_Pos (13U)
7650#define FMC_BCR3_WAITEN_Msk (0x1UL << FMC_BCR3_WAITEN_Pos)
7651#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk
7652#define FMC_BCR3_EXTMOD_Pos (14U)
7653#define FMC_BCR3_EXTMOD_Msk (0x1UL << FMC_BCR3_EXTMOD_Pos)
7654#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk
7655#define FMC_BCR3_ASYNCWAIT_Pos (15U)
7656#define FMC_BCR3_ASYNCWAIT_Msk (0x1UL << FMC_BCR3_ASYNCWAIT_Pos)
7657#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk
7658#define FMC_BCR3_CPSIZE_Pos (16U)
7659#define FMC_BCR3_CPSIZE_Msk (0x7UL << FMC_BCR3_CPSIZE_Pos)
7660#define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk
7661#define FMC_BCR3_CPSIZE_0 (0x1UL << FMC_BCR3_CPSIZE_Pos)
7662#define FMC_BCR3_CPSIZE_1 (0x2UL << FMC_BCR3_CPSIZE_Pos)
7663#define FMC_BCR3_CPSIZE_2 (0x4UL << FMC_BCR3_CPSIZE_Pos)
7664#define FMC_BCR3_CBURSTRW_Pos (19U)
7665#define FMC_BCR3_CBURSTRW_Msk (0x1UL << FMC_BCR3_CBURSTRW_Pos)
7666#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk
7667
7668/****************** Bit definition for FMC_BCR4 register *******************/
7669#define FMC_BCR4_MBKEN_Pos (0U)
7670#define FMC_BCR4_MBKEN_Msk (0x1UL << FMC_BCR4_MBKEN_Pos)
7671#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk
7672#define FMC_BCR4_MUXEN_Pos (1U)
7673#define FMC_BCR4_MUXEN_Msk (0x1UL << FMC_BCR4_MUXEN_Pos)
7674#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk
7675
7676#define FMC_BCR4_MTYP_Pos (2U)
7677#define FMC_BCR4_MTYP_Msk (0x3UL << FMC_BCR4_MTYP_Pos)
7678#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk
7679#define FMC_BCR4_MTYP_0 (0x1UL << FMC_BCR4_MTYP_Pos)
7680#define FMC_BCR4_MTYP_1 (0x2UL << FMC_BCR4_MTYP_Pos)
7681
7682#define FMC_BCR4_MWID_Pos (4U)
7683#define FMC_BCR4_MWID_Msk (0x3UL << FMC_BCR4_MWID_Pos)
7684#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk
7685#define FMC_BCR4_MWID_0 (0x1UL << FMC_BCR4_MWID_Pos)
7686#define FMC_BCR4_MWID_1 (0x2UL << FMC_BCR4_MWID_Pos)
7687
7688#define FMC_BCR4_FACCEN_Pos (6U)
7689#define FMC_BCR4_FACCEN_Msk (0x1UL << FMC_BCR4_FACCEN_Pos)
7690#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk
7691#define FMC_BCR4_BURSTEN_Pos (8U)
7692#define FMC_BCR4_BURSTEN_Msk (0x1UL << FMC_BCR4_BURSTEN_Pos)
7693#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk
7694#define FMC_BCR4_WAITPOL_Pos (9U)
7695#define FMC_BCR4_WAITPOL_Msk (0x1UL << FMC_BCR4_WAITPOL_Pos)
7696#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk
7697#define FMC_BCR4_WRAPMOD_Pos (10U)
7698#define FMC_BCR4_WRAPMOD_Msk (0x1UL << FMC_BCR4_WRAPMOD_Pos)
7699#define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk
7700#define FMC_BCR4_WAITCFG_Pos (11U)
7701#define FMC_BCR4_WAITCFG_Msk (0x1UL << FMC_BCR4_WAITCFG_Pos)
7702#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk
7703#define FMC_BCR4_WREN_Pos (12U)
7704#define FMC_BCR4_WREN_Msk (0x1UL << FMC_BCR4_WREN_Pos)
7705#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk
7706#define FMC_BCR4_WAITEN_Pos (13U)
7707#define FMC_BCR4_WAITEN_Msk (0x1UL << FMC_BCR4_WAITEN_Pos)
7708#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk
7709#define FMC_BCR4_EXTMOD_Pos (14U)
7710#define FMC_BCR4_EXTMOD_Msk (0x1UL << FMC_BCR4_EXTMOD_Pos)
7711#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk
7712#define FMC_BCR4_ASYNCWAIT_Pos (15U)
7713#define FMC_BCR4_ASYNCWAIT_Msk (0x1UL << FMC_BCR4_ASYNCWAIT_Pos)
7714#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk
7715#define FMC_BCR4_CPSIZE_Pos (16U)
7716#define FMC_BCR4_CPSIZE_Msk (0x7UL << FMC_BCR4_CPSIZE_Pos)
7717#define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk
7718#define FMC_BCR4_CPSIZE_0 (0x1UL << FMC_BCR4_CPSIZE_Pos)
7719#define FMC_BCR4_CPSIZE_1 (0x2UL << FMC_BCR4_CPSIZE_Pos)
7720#define FMC_BCR4_CPSIZE_2 (0x4UL << FMC_BCR4_CPSIZE_Pos)
7721#define FMC_BCR4_CBURSTRW_Pos (19U)
7722#define FMC_BCR4_CBURSTRW_Msk (0x1UL << FMC_BCR4_CBURSTRW_Pos)
7723#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk
7724
7725/****************** Bit definition for FMC_BTR1 register ******************/
7726#define FMC_BTR1_ADDSET_Pos (0U)
7727#define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos)
7728#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk
7729#define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos)
7730#define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos)
7731#define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos)
7732#define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos)
7733
7734#define FMC_BTR1_ADDHLD_Pos (4U)
7735#define FMC_BTR1_ADDHLD_Msk (0xFUL << FMC_BTR1_ADDHLD_Pos)
7736#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk
7737#define FMC_BTR1_ADDHLD_0 (0x1UL << FMC_BTR1_ADDHLD_Pos)
7738#define FMC_BTR1_ADDHLD_1 (0x2UL << FMC_BTR1_ADDHLD_Pos)
7739#define FMC_BTR1_ADDHLD_2 (0x4UL << FMC_BTR1_ADDHLD_Pos)
7740#define FMC_BTR1_ADDHLD_3 (0x8UL << FMC_BTR1_ADDHLD_Pos)
7741
7742#define FMC_BTR1_DATAST_Pos (8U)
7743#define FMC_BTR1_DATAST_Msk (0xFFUL << FMC_BTR1_DATAST_Pos)
7744#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk
7745#define FMC_BTR1_DATAST_0 (0x01UL << FMC_BTR1_DATAST_Pos)
7746#define FMC_BTR1_DATAST_1 (0x02UL << FMC_BTR1_DATAST_Pos)
7747#define FMC_BTR1_DATAST_2 (0x04UL << FMC_BTR1_DATAST_Pos)
7748#define FMC_BTR1_DATAST_3 (0x08UL << FMC_BTR1_DATAST_Pos)
7749#define FMC_BTR1_DATAST_4 (0x10UL << FMC_BTR1_DATAST_Pos)
7750#define FMC_BTR1_DATAST_5 (0x20UL << FMC_BTR1_DATAST_Pos)
7751#define FMC_BTR1_DATAST_6 (0x40UL << FMC_BTR1_DATAST_Pos)
7752#define FMC_BTR1_DATAST_7 (0x80UL << FMC_BTR1_DATAST_Pos)
7753
7754#define FMC_BTR1_BUSTURN_Pos (16U)
7755#define FMC_BTR1_BUSTURN_Msk (0xFUL << FMC_BTR1_BUSTURN_Pos)
7756#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk
7757#define FMC_BTR1_BUSTURN_0 (0x1UL << FMC_BTR1_BUSTURN_Pos)
7758#define FMC_BTR1_BUSTURN_1 (0x2UL << FMC_BTR1_BUSTURN_Pos)
7759#define FMC_BTR1_BUSTURN_2 (0x4UL << FMC_BTR1_BUSTURN_Pos)
7760#define FMC_BTR1_BUSTURN_3 (0x8UL << FMC_BTR1_BUSTURN_Pos)
7761
7762#define FMC_BTR1_CLKDIV_Pos (20U)
7763#define FMC_BTR1_CLKDIV_Msk (0xFUL << FMC_BTR1_CLKDIV_Pos)
7764#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk
7765#define FMC_BTR1_CLKDIV_0 (0x1UL << FMC_BTR1_CLKDIV_Pos)
7766#define FMC_BTR1_CLKDIV_1 (0x2UL << FMC_BTR1_CLKDIV_Pos)
7767#define FMC_BTR1_CLKDIV_2 (0x4UL << FMC_BTR1_CLKDIV_Pos)
7768#define FMC_BTR1_CLKDIV_3 (0x8UL << FMC_BTR1_CLKDIV_Pos)
7769
7770#define FMC_BTR1_DATLAT_Pos (24U)
7771#define FMC_BTR1_DATLAT_Msk (0xFUL << FMC_BTR1_DATLAT_Pos)
7772#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk
7773#define FMC_BTR1_DATLAT_0 (0x1UL << FMC_BTR1_DATLAT_Pos)
7774#define FMC_BTR1_DATLAT_1 (0x2UL << FMC_BTR1_DATLAT_Pos)
7775#define FMC_BTR1_DATLAT_2 (0x4UL << FMC_BTR1_DATLAT_Pos)
7776#define FMC_BTR1_DATLAT_3 (0x8UL << FMC_BTR1_DATLAT_Pos)
7777
7778#define FMC_BTR1_ACCMOD_Pos (28U)
7779#define FMC_BTR1_ACCMOD_Msk (0x3UL << FMC_BTR1_ACCMOD_Pos)
7780#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk
7781#define FMC_BTR1_ACCMOD_0 (0x1UL << FMC_BTR1_ACCMOD_Pos)
7782#define FMC_BTR1_ACCMOD_1 (0x2UL << FMC_BTR1_ACCMOD_Pos)
7783
7784/****************** Bit definition for FMC_BTR2 register *******************/
7785#define FMC_BTR2_ADDSET_Pos (0U)
7786#define FMC_BTR2_ADDSET_Msk (0xFUL << FMC_BTR2_ADDSET_Pos)
7787#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk
7788#define FMC_BTR2_ADDSET_0 (0x1UL << FMC_BTR2_ADDSET_Pos)
7789#define FMC_BTR2_ADDSET_1 (0x2UL << FMC_BTR2_ADDSET_Pos)
7790#define FMC_BTR2_ADDSET_2 (0x4UL << FMC_BTR2_ADDSET_Pos)
7791#define FMC_BTR2_ADDSET_3 (0x8UL << FMC_BTR2_ADDSET_Pos)
7792
7793#define FMC_BTR2_ADDHLD_Pos (4U)
7794#define FMC_BTR2_ADDHLD_Msk (0xFUL << FMC_BTR2_ADDHLD_Pos)
7795#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk
7796#define FMC_BTR2_ADDHLD_0 (0x1UL << FMC_BTR2_ADDHLD_Pos)
7797#define FMC_BTR2_ADDHLD_1 (0x2UL << FMC_BTR2_ADDHLD_Pos)
7798#define FMC_BTR2_ADDHLD_2 (0x4UL << FMC_BTR2_ADDHLD_Pos)
7799#define FMC_BTR2_ADDHLD_3 (0x8UL << FMC_BTR2_ADDHLD_Pos)
7800
7801#define FMC_BTR2_DATAST_Pos (8U)
7802#define FMC_BTR2_DATAST_Msk (0xFFUL << FMC_BTR2_DATAST_Pos)
7803#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk
7804#define FMC_BTR2_DATAST_0 (0x01UL << FMC_BTR2_DATAST_Pos)
7805#define FMC_BTR2_DATAST_1 (0x02UL << FMC_BTR2_DATAST_Pos)
7806#define FMC_BTR2_DATAST_2 (0x04UL << FMC_BTR2_DATAST_Pos)
7807#define FMC_BTR2_DATAST_3 (0x08UL << FMC_BTR2_DATAST_Pos)
7808#define FMC_BTR2_DATAST_4 (0x10UL << FMC_BTR2_DATAST_Pos)
7809#define FMC_BTR2_DATAST_5 (0x20UL << FMC_BTR2_DATAST_Pos)
7810#define FMC_BTR2_DATAST_6 (0x40UL << FMC_BTR2_DATAST_Pos)
7811#define FMC_BTR2_DATAST_7 (0x80UL << FMC_BTR2_DATAST_Pos)
7812
7813#define FMC_BTR2_BUSTURN_Pos (16U)
7814#define FMC_BTR2_BUSTURN_Msk (0xFUL << FMC_BTR2_BUSTURN_Pos)
7815#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk
7816#define FMC_BTR2_BUSTURN_0 (0x1UL << FMC_BTR2_BUSTURN_Pos)
7817#define FMC_BTR2_BUSTURN_1 (0x2UL << FMC_BTR2_BUSTURN_Pos)
7818#define FMC_BTR2_BUSTURN_2 (0x4UL << FMC_BTR2_BUSTURN_Pos)
7819#define FMC_BTR2_BUSTURN_3 (0x8UL << FMC_BTR2_BUSTURN_Pos)
7820
7821#define FMC_BTR2_CLKDIV_Pos (20U)
7822#define FMC_BTR2_CLKDIV_Msk (0xFUL << FMC_BTR2_CLKDIV_Pos)
7823#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk
7824#define FMC_BTR2_CLKDIV_0 (0x1UL << FMC_BTR2_CLKDIV_Pos)
7825#define FMC_BTR2_CLKDIV_1 (0x2UL << FMC_BTR2_CLKDIV_Pos)
7826#define FMC_BTR2_CLKDIV_2 (0x4UL << FMC_BTR2_CLKDIV_Pos)
7827#define FMC_BTR2_CLKDIV_3 (0x8UL << FMC_BTR2_CLKDIV_Pos)
7828
7829#define FMC_BTR2_DATLAT_Pos (24U)
7830#define FMC_BTR2_DATLAT_Msk (0xFUL << FMC_BTR2_DATLAT_Pos)
7831#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk
7832#define FMC_BTR2_DATLAT_0 (0x1UL << FMC_BTR2_DATLAT_Pos)
7833#define FMC_BTR2_DATLAT_1 (0x2UL << FMC_BTR2_DATLAT_Pos)
7834#define FMC_BTR2_DATLAT_2 (0x4UL << FMC_BTR2_DATLAT_Pos)
7835#define FMC_BTR2_DATLAT_3 (0x8UL << FMC_BTR2_DATLAT_Pos)
7836
7837#define FMC_BTR2_ACCMOD_Pos (28U)
7838#define FMC_BTR2_ACCMOD_Msk (0x3UL << FMC_BTR2_ACCMOD_Pos)
7839#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk
7840#define FMC_BTR2_ACCMOD_0 (0x1UL << FMC_BTR2_ACCMOD_Pos)
7841#define FMC_BTR2_ACCMOD_1 (0x2UL << FMC_BTR2_ACCMOD_Pos)
7842
7843/******************* Bit definition for FMC_BTR3 register *******************/
7844#define FMC_BTR3_ADDSET_Pos (0U)
7845#define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos)
7846#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk
7847#define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos)
7848#define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos)
7849#define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos)
7850#define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos)
7851
7852#define FMC_BTR3_ADDHLD_Pos (4U)
7853#define FMC_BTR3_ADDHLD_Msk (0xFUL << FMC_BTR3_ADDHLD_Pos)
7854#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk
7855#define FMC_BTR3_ADDHLD_0 (0x1UL << FMC_BTR3_ADDHLD_Pos)
7856#define FMC_BTR3_ADDHLD_1 (0x2UL << FMC_BTR3_ADDHLD_Pos)
7857#define FMC_BTR3_ADDHLD_2 (0x4UL << FMC_BTR3_ADDHLD_Pos)
7858#define FMC_BTR3_ADDHLD_3 (0x8UL << FMC_BTR3_ADDHLD_Pos)
7859
7860#define FMC_BTR3_DATAST_Pos (8U)
7861#define FMC_BTR3_DATAST_Msk (0xFFUL << FMC_BTR3_DATAST_Pos)
7862#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk
7863#define FMC_BTR3_DATAST_0 (0x01UL << FMC_BTR3_DATAST_Pos)
7864#define FMC_BTR3_DATAST_1 (0x02UL << FMC_BTR3_DATAST_Pos)
7865#define FMC_BTR3_DATAST_2 (0x04UL << FMC_BTR3_DATAST_Pos)
7866#define FMC_BTR3_DATAST_3 (0x08UL << FMC_BTR3_DATAST_Pos)
7867#define FMC_BTR3_DATAST_4 (0x10UL << FMC_BTR3_DATAST_Pos)
7868#define FMC_BTR3_DATAST_5 (0x20UL << FMC_BTR3_DATAST_Pos)
7869#define FMC_BTR3_DATAST_6 (0x40UL << FMC_BTR3_DATAST_Pos)
7870#define FMC_BTR3_DATAST_7 (0x80UL << FMC_BTR3_DATAST_Pos)
7871
7872#define FMC_BTR3_BUSTURN_Pos (16U)
7873#define FMC_BTR3_BUSTURN_Msk (0xFUL << FMC_BTR3_BUSTURN_Pos)
7874#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk
7875#define FMC_BTR3_BUSTURN_0 (0x1UL << FMC_BTR3_BUSTURN_Pos)
7876#define FMC_BTR3_BUSTURN_1 (0x2UL << FMC_BTR3_BUSTURN_Pos)
7877#define FMC_BTR3_BUSTURN_2 (0x4UL << FMC_BTR3_BUSTURN_Pos)
7878#define FMC_BTR3_BUSTURN_3 (0x8UL << FMC_BTR3_BUSTURN_Pos)
7879
7880#define FMC_BTR3_CLKDIV_Pos (20U)
7881#define FMC_BTR3_CLKDIV_Msk (0xFUL << FMC_BTR3_CLKDIV_Pos)
7882#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk
7883#define FMC_BTR3_CLKDIV_0 (0x1UL << FMC_BTR3_CLKDIV_Pos)
7884#define FMC_BTR3_CLKDIV_1 (0x2UL << FMC_BTR3_CLKDIV_Pos)
7885#define FMC_BTR3_CLKDIV_2 (0x4UL << FMC_BTR3_CLKDIV_Pos)
7886#define FMC_BTR3_CLKDIV_3 (0x8UL << FMC_BTR3_CLKDIV_Pos)
7887
7888#define FMC_BTR3_DATLAT_Pos (24U)
7889#define FMC_BTR3_DATLAT_Msk (0xFUL << FMC_BTR3_DATLAT_Pos)
7890#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk
7891#define FMC_BTR3_DATLAT_0 (0x1UL << FMC_BTR3_DATLAT_Pos)
7892#define FMC_BTR3_DATLAT_1 (0x2UL << FMC_BTR3_DATLAT_Pos)
7893#define FMC_BTR3_DATLAT_2 (0x4UL << FMC_BTR3_DATLAT_Pos)
7894#define FMC_BTR3_DATLAT_3 (0x8UL << FMC_BTR3_DATLAT_Pos)
7895
7896#define FMC_BTR3_ACCMOD_Pos (28U)
7897#define FMC_BTR3_ACCMOD_Msk (0x3UL << FMC_BTR3_ACCMOD_Pos)
7898#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk
7899#define FMC_BTR3_ACCMOD_0 (0x1UL << FMC_BTR3_ACCMOD_Pos)
7900#define FMC_BTR3_ACCMOD_1 (0x2UL << FMC_BTR3_ACCMOD_Pos)
7901
7902/****************** Bit definition for FMC_BTR4 register *******************/
7903#define FMC_BTR4_ADDSET_Pos (0U)
7904#define FMC_BTR4_ADDSET_Msk (0xFUL << FMC_BTR4_ADDSET_Pos)
7905#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk
7906#define FMC_BTR4_ADDSET_0 (0x1UL << FMC_BTR4_ADDSET_Pos)
7907#define FMC_BTR4_ADDSET_1 (0x2UL << FMC_BTR4_ADDSET_Pos)
7908#define FMC_BTR4_ADDSET_2 (0x4UL << FMC_BTR4_ADDSET_Pos)
7909#define FMC_BTR4_ADDSET_3 (0x8UL << FMC_BTR4_ADDSET_Pos)
7910
7911#define FMC_BTR4_ADDHLD_Pos (4U)
7912#define FMC_BTR4_ADDHLD_Msk (0xFUL << FMC_BTR4_ADDHLD_Pos)
7913#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk
7914#define FMC_BTR4_ADDHLD_0 (0x1UL << FMC_BTR4_ADDHLD_Pos)
7915#define FMC_BTR4_ADDHLD_1 (0x2UL << FMC_BTR4_ADDHLD_Pos)
7916#define FMC_BTR4_ADDHLD_2 (0x4UL << FMC_BTR4_ADDHLD_Pos)
7917#define FMC_BTR4_ADDHLD_3 (0x8UL << FMC_BTR4_ADDHLD_Pos)
7918
7919#define FMC_BTR4_DATAST_Pos (8U)
7920#define FMC_BTR4_DATAST_Msk (0xFFUL << FMC_BTR4_DATAST_Pos)
7921#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk
7922#define FMC_BTR4_DATAST_0 (0x01UL << FMC_BTR4_DATAST_Pos)
7923#define FMC_BTR4_DATAST_1 (0x02UL << FMC_BTR4_DATAST_Pos)
7924#define FMC_BTR4_DATAST_2 (0x04UL << FMC_BTR4_DATAST_Pos)
7925#define FMC_BTR4_DATAST_3 (0x08UL << FMC_BTR4_DATAST_Pos)
7926#define FMC_BTR4_DATAST_4 (0x10UL << FMC_BTR4_DATAST_Pos)
7927#define FMC_BTR4_DATAST_5 (0x20UL << FMC_BTR4_DATAST_Pos)
7928#define FMC_BTR4_DATAST_6 (0x40UL << FMC_BTR4_DATAST_Pos)
7929#define FMC_BTR4_DATAST_7 (0x80UL << FMC_BTR4_DATAST_Pos)
7930
7931#define FMC_BTR4_BUSTURN_Pos (16U)
7932#define FMC_BTR4_BUSTURN_Msk (0xFUL << FMC_BTR4_BUSTURN_Pos)
7933#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk
7934#define FMC_BTR4_BUSTURN_0 (0x1UL << FMC_BTR4_BUSTURN_Pos)
7935#define FMC_BTR4_BUSTURN_1 (0x2UL << FMC_BTR4_BUSTURN_Pos)
7936#define FMC_BTR4_BUSTURN_2 (0x4UL << FMC_BTR4_BUSTURN_Pos)
7937#define FMC_BTR4_BUSTURN_3 (0x8UL << FMC_BTR4_BUSTURN_Pos)
7938
7939#define FMC_BTR4_CLKDIV_Pos (20U)
7940#define FMC_BTR4_CLKDIV_Msk (0xFUL << FMC_BTR4_CLKDIV_Pos)
7941#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk
7942#define FMC_BTR4_CLKDIV_0 (0x1UL << FMC_BTR4_CLKDIV_Pos)
7943#define FMC_BTR4_CLKDIV_1 (0x2UL << FMC_BTR4_CLKDIV_Pos)
7944#define FMC_BTR4_CLKDIV_2 (0x4UL << FMC_BTR4_CLKDIV_Pos)
7945#define FMC_BTR4_CLKDIV_3 (0x8UL << FMC_BTR4_CLKDIV_Pos)
7946
7947#define FMC_BTR4_DATLAT_Pos (24U)
7948#define FMC_BTR4_DATLAT_Msk (0xFUL << FMC_BTR4_DATLAT_Pos)
7949#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk
7950#define FMC_BTR4_DATLAT_0 (0x1UL << FMC_BTR4_DATLAT_Pos)
7951#define FMC_BTR4_DATLAT_1 (0x2UL << FMC_BTR4_DATLAT_Pos)
7952#define FMC_BTR4_DATLAT_2 (0x4UL << FMC_BTR4_DATLAT_Pos)
7953#define FMC_BTR4_DATLAT_3 (0x8UL << FMC_BTR4_DATLAT_Pos)
7954
7955#define FMC_BTR4_ACCMOD_Pos (28U)
7956#define FMC_BTR4_ACCMOD_Msk (0x3UL << FMC_BTR4_ACCMOD_Pos)
7957#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk
7958#define FMC_BTR4_ACCMOD_0 (0x1UL << FMC_BTR4_ACCMOD_Pos)
7959#define FMC_BTR4_ACCMOD_1 (0x2UL << FMC_BTR4_ACCMOD_Pos)
7960
7961/****************** Bit definition for FMC_BWTR1 register ******************/
7962#define FMC_BWTR1_ADDSET_Pos (0U)
7963#define FMC_BWTR1_ADDSET_Msk (0xFUL << FMC_BWTR1_ADDSET_Pos)
7964#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk
7965#define FMC_BWTR1_ADDSET_0 (0x1UL << FMC_BWTR1_ADDSET_Pos)
7966#define FMC_BWTR1_ADDSET_1 (0x2UL << FMC_BWTR1_ADDSET_Pos)
7967#define FMC_BWTR1_ADDSET_2 (0x4UL << FMC_BWTR1_ADDSET_Pos)
7968#define FMC_BWTR1_ADDSET_3 (0x8UL << FMC_BWTR1_ADDSET_Pos)
7969
7970#define FMC_BWTR1_ADDHLD_Pos (4U)
7971#define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos)
7972#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk
7973#define FMC_BWTR1_ADDHLD_0 (0x1UL << FMC_BWTR1_ADDHLD_Pos)
7974#define FMC_BWTR1_ADDHLD_1 (0x2UL << FMC_BWTR1_ADDHLD_Pos)
7975#define FMC_BWTR1_ADDHLD_2 (0x4UL << FMC_BWTR1_ADDHLD_Pos)
7976#define FMC_BWTR1_ADDHLD_3 (0x8UL << FMC_BWTR1_ADDHLD_Pos)
7977
7978#define FMC_BWTR1_DATAST_Pos (8U)
7979#define FMC_BWTR1_DATAST_Msk (0xFFUL << FMC_BWTR1_DATAST_Pos)
7980#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk
7981#define FMC_BWTR1_DATAST_0 (0x01UL << FMC_BWTR1_DATAST_Pos)
7982#define FMC_BWTR1_DATAST_1 (0x02UL << FMC_BWTR1_DATAST_Pos)
7983#define FMC_BWTR1_DATAST_2 (0x04UL << FMC_BWTR1_DATAST_Pos)
7984#define FMC_BWTR1_DATAST_3 (0x08UL << FMC_BWTR1_DATAST_Pos)
7985#define FMC_BWTR1_DATAST_4 (0x10UL << FMC_BWTR1_DATAST_Pos)
7986#define FMC_BWTR1_DATAST_5 (0x20UL << FMC_BWTR1_DATAST_Pos)
7987#define FMC_BWTR1_DATAST_6 (0x40UL << FMC_BWTR1_DATAST_Pos)
7988#define FMC_BWTR1_DATAST_7 (0x80UL << FMC_BWTR1_DATAST_Pos)
7989
7990#define FMC_BWTR1_BUSTURN_Pos (16U)
7991#define FMC_BWTR1_BUSTURN_Msk (0xFUL << FMC_BWTR1_BUSTURN_Pos)
7992#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk
7993#define FMC_BWTR1_BUSTURN_0 (0x1UL << FMC_BWTR1_BUSTURN_Pos)
7994#define FMC_BWTR1_BUSTURN_1 (0x2UL << FMC_BWTR1_BUSTURN_Pos)
7995#define FMC_BWTR1_BUSTURN_2 (0x4UL << FMC_BWTR1_BUSTURN_Pos)
7996#define FMC_BWTR1_BUSTURN_3 (0x8UL << FMC_BWTR1_BUSTURN_Pos)
7997
7998#define FMC_BWTR1_ACCMOD_Pos (28U)
7999#define FMC_BWTR1_ACCMOD_Msk (0x3UL << FMC_BWTR1_ACCMOD_Pos)
8000#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk
8001#define FMC_BWTR1_ACCMOD_0 (0x1UL << FMC_BWTR1_ACCMOD_Pos)
8002#define FMC_BWTR1_ACCMOD_1 (0x2UL << FMC_BWTR1_ACCMOD_Pos)
8003
8004/****************** Bit definition for FMC_BWTR2 register ******************/
8005#define FMC_BWTR2_ADDSET_Pos (0U)
8006#define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos)
8007#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk
8008#define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos)
8009#define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos)
8010#define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos)
8011#define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos)
8012
8013#define FMC_BWTR2_ADDHLD_Pos (4U)
8014#define FMC_BWTR2_ADDHLD_Msk (0xFUL << FMC_BWTR2_ADDHLD_Pos)
8015#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk
8016#define FMC_BWTR2_ADDHLD_0 (0x1UL << FMC_BWTR2_ADDHLD_Pos)
8017#define FMC_BWTR2_ADDHLD_1 (0x2UL << FMC_BWTR2_ADDHLD_Pos)
8018#define FMC_BWTR2_ADDHLD_2 (0x4UL << FMC_BWTR2_ADDHLD_Pos)
8019#define FMC_BWTR2_ADDHLD_3 (0x8UL << FMC_BWTR2_ADDHLD_Pos)
8020
8021#define FMC_BWTR2_DATAST_Pos (8U)
8022#define FMC_BWTR2_DATAST_Msk (0xFFUL << FMC_BWTR2_DATAST_Pos)
8023#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk
8024#define FMC_BWTR2_DATAST_0 (0x01UL << FMC_BWTR2_DATAST_Pos)
8025#define FMC_BWTR2_DATAST_1 (0x02UL << FMC_BWTR2_DATAST_Pos)
8026#define FMC_BWTR2_DATAST_2 (0x04UL << FMC_BWTR2_DATAST_Pos)
8027#define FMC_BWTR2_DATAST_3 (0x08UL << FMC_BWTR2_DATAST_Pos)
8028#define FMC_BWTR2_DATAST_4 (0x10UL << FMC_BWTR2_DATAST_Pos)
8029#define FMC_BWTR2_DATAST_5 (0x20UL << FMC_BWTR2_DATAST_Pos)
8030#define FMC_BWTR2_DATAST_6 (0x40UL << FMC_BWTR2_DATAST_Pos)
8031#define FMC_BWTR2_DATAST_7 (0x80UL << FMC_BWTR2_DATAST_Pos)
8032
8033#define FMC_BWTR2_BUSTURN_Pos (16U)
8034#define FMC_BWTR2_BUSTURN_Msk (0xFUL << FMC_BWTR2_BUSTURN_Pos)
8035#define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk
8036#define FMC_BWTR2_BUSTURN_0 (0x1UL << FMC_BWTR2_BUSTURN_Pos)
8037#define FMC_BWTR2_BUSTURN_1 (0x2UL << FMC_BWTR2_BUSTURN_Pos)
8038#define FMC_BWTR2_BUSTURN_2 (0x4UL << FMC_BWTR2_BUSTURN_Pos)
8039#define FMC_BWTR2_BUSTURN_3 (0x8UL << FMC_BWTR2_BUSTURN_Pos)
8040
8041#define FMC_BWTR2_ACCMOD_Pos (28U)
8042#define FMC_BWTR2_ACCMOD_Msk (0x3UL << FMC_BWTR2_ACCMOD_Pos)
8043#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk
8044#define FMC_BWTR2_ACCMOD_0 (0x1UL << FMC_BWTR2_ACCMOD_Pos)
8045#define FMC_BWTR2_ACCMOD_1 (0x2UL << FMC_BWTR2_ACCMOD_Pos)
8046
8047/****************** Bit definition for FMC_BWTR3 register ******************/
8048#define FMC_BWTR3_ADDSET_Pos (0U)
8049#define FMC_BWTR3_ADDSET_Msk (0xFUL << FMC_BWTR3_ADDSET_Pos)
8050#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk
8051#define FMC_BWTR3_ADDSET_0 (0x1UL << FMC_BWTR3_ADDSET_Pos)
8052#define FMC_BWTR3_ADDSET_1 (0x2UL << FMC_BWTR3_ADDSET_Pos)
8053#define FMC_BWTR3_ADDSET_2 (0x4UL << FMC_BWTR3_ADDSET_Pos)
8054#define FMC_BWTR3_ADDSET_3 (0x8UL << FMC_BWTR3_ADDSET_Pos)
8055
8056#define FMC_BWTR3_ADDHLD_Pos (4U)
8057#define FMC_BWTR3_ADDHLD_Msk (0xFUL << FMC_BWTR3_ADDHLD_Pos)
8058#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk
8059#define FMC_BWTR3_ADDHLD_0 (0x1UL << FMC_BWTR3_ADDHLD_Pos)
8060#define FMC_BWTR3_ADDHLD_1 (0x2UL << FMC_BWTR3_ADDHLD_Pos)
8061#define FMC_BWTR3_ADDHLD_2 (0x4UL << FMC_BWTR3_ADDHLD_Pos)
8062#define FMC_BWTR3_ADDHLD_3 (0x8UL << FMC_BWTR3_ADDHLD_Pos)
8063
8064#define FMC_BWTR3_DATAST_Pos (8U)
8065#define FMC_BWTR3_DATAST_Msk (0xFFUL << FMC_BWTR3_DATAST_Pos)
8066#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk
8067#define FMC_BWTR3_DATAST_0 (0x01UL << FMC_BWTR3_DATAST_Pos)
8068#define FMC_BWTR3_DATAST_1 (0x02UL << FMC_BWTR3_DATAST_Pos)
8069#define FMC_BWTR3_DATAST_2 (0x04UL << FMC_BWTR3_DATAST_Pos)
8070#define FMC_BWTR3_DATAST_3 (0x08UL << FMC_BWTR3_DATAST_Pos)
8071#define FMC_BWTR3_DATAST_4 (0x10UL << FMC_BWTR3_DATAST_Pos)
8072#define FMC_BWTR3_DATAST_5 (0x20UL << FMC_BWTR3_DATAST_Pos)
8073#define FMC_BWTR3_DATAST_6 (0x40UL << FMC_BWTR3_DATAST_Pos)
8074#define FMC_BWTR3_DATAST_7 (0x80UL << FMC_BWTR3_DATAST_Pos)
8075
8076#define FMC_BWTR3_BUSTURN_Pos (16U)
8077#define FMC_BWTR3_BUSTURN_Msk (0xFUL << FMC_BWTR3_BUSTURN_Pos)
8078#define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk
8079#define FMC_BWTR3_BUSTURN_0 (0x1UL << FMC_BWTR3_BUSTURN_Pos)
8080#define FMC_BWTR3_BUSTURN_1 (0x2UL << FMC_BWTR3_BUSTURN_Pos)
8081#define FMC_BWTR3_BUSTURN_2 (0x4UL << FMC_BWTR3_BUSTURN_Pos)
8082#define FMC_BWTR3_BUSTURN_3 (0x8UL << FMC_BWTR3_BUSTURN_Pos)
8083
8084#define FMC_BWTR3_ACCMOD_Pos (28U)
8085#define FMC_BWTR3_ACCMOD_Msk (0x3UL << FMC_BWTR3_ACCMOD_Pos)
8086#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk
8087#define FMC_BWTR3_ACCMOD_0 (0x1UL << FMC_BWTR3_ACCMOD_Pos)
8088#define FMC_BWTR3_ACCMOD_1 (0x2UL << FMC_BWTR3_ACCMOD_Pos)
8089
8090/****************** Bit definition for FMC_BWTR4 register ******************/
8091#define FMC_BWTR4_ADDSET_Pos (0U)
8092#define FMC_BWTR4_ADDSET_Msk (0xFUL << FMC_BWTR4_ADDSET_Pos)
8093#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk
8094#define FMC_BWTR4_ADDSET_0 (0x1UL << FMC_BWTR4_ADDSET_Pos)
8095#define FMC_BWTR4_ADDSET_1 (0x2UL << FMC_BWTR4_ADDSET_Pos)
8096#define FMC_BWTR4_ADDSET_2 (0x4UL << FMC_BWTR4_ADDSET_Pos)
8097#define FMC_BWTR4_ADDSET_3 (0x8UL << FMC_BWTR4_ADDSET_Pos)
8098
8099#define FMC_BWTR4_ADDHLD_Pos (4U)
8100#define FMC_BWTR4_ADDHLD_Msk (0xFUL << FMC_BWTR4_ADDHLD_Pos)
8101#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk
8102#define FMC_BWTR4_ADDHLD_0 (0x1UL << FMC_BWTR4_ADDHLD_Pos)
8103#define FMC_BWTR4_ADDHLD_1 (0x2UL << FMC_BWTR4_ADDHLD_Pos)
8104#define FMC_BWTR4_ADDHLD_2 (0x4UL << FMC_BWTR4_ADDHLD_Pos)
8105#define FMC_BWTR4_ADDHLD_3 (0x8UL << FMC_BWTR4_ADDHLD_Pos)
8106
8107#define FMC_BWTR4_DATAST_Pos (8U)
8108#define FMC_BWTR4_DATAST_Msk (0xFFUL << FMC_BWTR4_DATAST_Pos)
8109#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk
8110#define FMC_BWTR4_DATAST_0 (0x01UL << FMC_BWTR4_DATAST_Pos)
8111#define FMC_BWTR4_DATAST_1 (0x02UL << FMC_BWTR4_DATAST_Pos)
8112#define FMC_BWTR4_DATAST_2 (0x04UL << FMC_BWTR4_DATAST_Pos)
8113#define FMC_BWTR4_DATAST_3 (0x08UL << FMC_BWTR4_DATAST_Pos)
8114#define FMC_BWTR4_DATAST_4 (0x10UL << FMC_BWTR4_DATAST_Pos)
8115#define FMC_BWTR4_DATAST_5 (0x20UL << FMC_BWTR4_DATAST_Pos)
8116#define FMC_BWTR4_DATAST_6 (0x40UL << FMC_BWTR4_DATAST_Pos)
8117#define FMC_BWTR4_DATAST_7 (0x80UL << FMC_BWTR4_DATAST_Pos)
8118
8119#define FMC_BWTR4_BUSTURN_Pos (16U)
8120#define FMC_BWTR4_BUSTURN_Msk (0xFUL << FMC_BWTR4_BUSTURN_Pos)
8121#define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk
8122#define FMC_BWTR4_BUSTURN_0 (0x1UL << FMC_BWTR4_BUSTURN_Pos)
8123#define FMC_BWTR4_BUSTURN_1 (0x2UL << FMC_BWTR4_BUSTURN_Pos)
8124#define FMC_BWTR4_BUSTURN_2 (0x4UL << FMC_BWTR4_BUSTURN_Pos)
8125#define FMC_BWTR4_BUSTURN_3 (0x8UL << FMC_BWTR4_BUSTURN_Pos)
8126
8127#define FMC_BWTR4_ACCMOD_Pos (28U)
8128#define FMC_BWTR4_ACCMOD_Msk (0x3UL << FMC_BWTR4_ACCMOD_Pos)
8129#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk
8130#define FMC_BWTR4_ACCMOD_0 (0x1UL << FMC_BWTR4_ACCMOD_Pos)
8131#define FMC_BWTR4_ACCMOD_1 (0x2UL << FMC_BWTR4_ACCMOD_Pos)
8132
8133/****************** Bit definition for FMC_PCR2 register *******************/
8134
8135#define FMC_PCR2_PWAITEN_Pos (1U)
8136#define FMC_PCR2_PWAITEN_Msk (0x1UL << FMC_PCR2_PWAITEN_Pos)
8137#define FMC_PCR2_PWAITEN FMC_PCR2_PWAITEN_Msk
8138#define FMC_PCR2_PBKEN_Pos (2U)
8139#define FMC_PCR2_PBKEN_Msk (0x1UL << FMC_PCR2_PBKEN_Pos)
8140#define FMC_PCR2_PBKEN FMC_PCR2_PBKEN_Msk
8141#define FMC_PCR2_PTYP_Pos (3U)
8142#define FMC_PCR2_PTYP_Msk (0x1UL << FMC_PCR2_PTYP_Pos)
8143#define FMC_PCR2_PTYP FMC_PCR2_PTYP_Msk
8144
8145#define FMC_PCR2_PWID_Pos (4U)
8146#define FMC_PCR2_PWID_Msk (0x3UL << FMC_PCR2_PWID_Pos)
8147#define FMC_PCR2_PWID FMC_PCR2_PWID_Msk
8148#define FMC_PCR2_PWID_0 (0x1UL << FMC_PCR2_PWID_Pos)
8149#define FMC_PCR2_PWID_1 (0x2UL << FMC_PCR2_PWID_Pos)
8150
8151#define FMC_PCR2_ECCEN_Pos (6U)
8152#define FMC_PCR2_ECCEN_Msk (0x1UL << FMC_PCR2_ECCEN_Pos)
8153#define FMC_PCR2_ECCEN FMC_PCR2_ECCEN_Msk
8154
8155#define FMC_PCR2_TCLR_Pos (9U)
8156#define FMC_PCR2_TCLR_Msk (0xFUL << FMC_PCR2_TCLR_Pos)
8157#define FMC_PCR2_TCLR FMC_PCR2_TCLR_Msk
8158#define FMC_PCR2_TCLR_0 (0x1UL << FMC_PCR2_TCLR_Pos)
8159#define FMC_PCR2_TCLR_1 (0x2UL << FMC_PCR2_TCLR_Pos)
8160#define FMC_PCR2_TCLR_2 (0x4UL << FMC_PCR2_TCLR_Pos)
8161#define FMC_PCR2_TCLR_3 (0x8UL << FMC_PCR2_TCLR_Pos)
8162
8163#define FMC_PCR2_TAR_Pos (13U)
8164#define FMC_PCR2_TAR_Msk (0xFUL << FMC_PCR2_TAR_Pos)
8165#define FMC_PCR2_TAR FMC_PCR2_TAR_Msk
8166#define FMC_PCR2_TAR_0 (0x1UL << FMC_PCR2_TAR_Pos)
8167#define FMC_PCR2_TAR_1 (0x2UL << FMC_PCR2_TAR_Pos)
8168#define FMC_PCR2_TAR_2 (0x4UL << FMC_PCR2_TAR_Pos)
8169#define FMC_PCR2_TAR_3 (0x8UL << FMC_PCR2_TAR_Pos)
8170
8171#define FMC_PCR2_ECCPS_Pos (17U)
8172#define FMC_PCR2_ECCPS_Msk (0x7UL << FMC_PCR2_ECCPS_Pos)
8173#define FMC_PCR2_ECCPS FMC_PCR2_ECCPS_Msk
8174#define FMC_PCR2_ECCPS_0 (0x1UL << FMC_PCR2_ECCPS_Pos)
8175#define FMC_PCR2_ECCPS_1 (0x2UL << FMC_PCR2_ECCPS_Pos)
8176#define FMC_PCR2_ECCPS_2 (0x4UL << FMC_PCR2_ECCPS_Pos)
8177
8178/****************** Bit definition for FMC_PCR3 register *******************/
8179#define FMC_PCR3_PWAITEN_Pos (1U)
8180#define FMC_PCR3_PWAITEN_Msk (0x1UL << FMC_PCR3_PWAITEN_Pos)
8181#define FMC_PCR3_PWAITEN FMC_PCR3_PWAITEN_Msk
8182#define FMC_PCR3_PBKEN_Pos (2U)
8183#define FMC_PCR3_PBKEN_Msk (0x1UL << FMC_PCR3_PBKEN_Pos)
8184#define FMC_PCR3_PBKEN FMC_PCR3_PBKEN_Msk
8185#define FMC_PCR3_PTYP_Pos (3U)
8186#define FMC_PCR3_PTYP_Msk (0x1UL << FMC_PCR3_PTYP_Pos)
8187#define FMC_PCR3_PTYP FMC_PCR3_PTYP_Msk
8188
8189#define FMC_PCR3_PWID_Pos (4U)
8190#define FMC_PCR3_PWID_Msk (0x3UL << FMC_PCR3_PWID_Pos)
8191#define FMC_PCR3_PWID FMC_PCR3_PWID_Msk
8192#define FMC_PCR3_PWID_0 (0x1UL << FMC_PCR3_PWID_Pos)
8193#define FMC_PCR3_PWID_1 (0x2UL << FMC_PCR3_PWID_Pos)
8194
8195#define FMC_PCR3_ECCEN_Pos (6U)
8196#define FMC_PCR3_ECCEN_Msk (0x1UL << FMC_PCR3_ECCEN_Pos)
8197#define FMC_PCR3_ECCEN FMC_PCR3_ECCEN_Msk
8198
8199#define FMC_PCR3_TCLR_Pos (9U)
8200#define FMC_PCR3_TCLR_Msk (0xFUL << FMC_PCR3_TCLR_Pos)
8201#define FMC_PCR3_TCLR FMC_PCR3_TCLR_Msk
8202#define FMC_PCR3_TCLR_0 (0x1UL << FMC_PCR3_TCLR_Pos)
8203#define FMC_PCR3_TCLR_1 (0x2UL << FMC_PCR3_TCLR_Pos)
8204#define FMC_PCR3_TCLR_2 (0x4UL << FMC_PCR3_TCLR_Pos)
8205#define FMC_PCR3_TCLR_3 (0x8UL << FMC_PCR3_TCLR_Pos)
8206
8207#define FMC_PCR3_TAR_Pos (13U)
8208#define FMC_PCR3_TAR_Msk (0xFUL << FMC_PCR3_TAR_Pos)
8209#define FMC_PCR3_TAR FMC_PCR3_TAR_Msk
8210#define FMC_PCR3_TAR_0 (0x1UL << FMC_PCR3_TAR_Pos)
8211#define FMC_PCR3_TAR_1 (0x2UL << FMC_PCR3_TAR_Pos)
8212#define FMC_PCR3_TAR_2 (0x4UL << FMC_PCR3_TAR_Pos)
8213#define FMC_PCR3_TAR_3 (0x8UL << FMC_PCR3_TAR_Pos)
8214
8215#define FMC_PCR3_ECCPS_Pos (17U)
8216#define FMC_PCR3_ECCPS_Msk (0x7UL << FMC_PCR3_ECCPS_Pos)
8217#define FMC_PCR3_ECCPS FMC_PCR3_ECCPS_Msk
8218#define FMC_PCR3_ECCPS_0 (0x1UL << FMC_PCR3_ECCPS_Pos)
8219#define FMC_PCR3_ECCPS_1 (0x2UL << FMC_PCR3_ECCPS_Pos)
8220#define FMC_PCR3_ECCPS_2 (0x4UL << FMC_PCR3_ECCPS_Pos)
8221
8222/****************** Bit definition for FMC_PCR4 register *******************/
8223#define FMC_PCR4_PWAITEN_Pos (1U)
8224#define FMC_PCR4_PWAITEN_Msk (0x1UL << FMC_PCR4_PWAITEN_Pos)
8225#define FMC_PCR4_PWAITEN FMC_PCR4_PWAITEN_Msk
8226#define FMC_PCR4_PBKEN_Pos (2U)
8227#define FMC_PCR4_PBKEN_Msk (0x1UL << FMC_PCR4_PBKEN_Pos)
8228#define FMC_PCR4_PBKEN FMC_PCR4_PBKEN_Msk
8229#define FMC_PCR4_PTYP_Pos (3U)
8230#define FMC_PCR4_PTYP_Msk (0x1UL << FMC_PCR4_PTYP_Pos)
8231#define FMC_PCR4_PTYP FMC_PCR4_PTYP_Msk
8232
8233#define FMC_PCR4_PWID_Pos (4U)
8234#define FMC_PCR4_PWID_Msk (0x3UL << FMC_PCR4_PWID_Pos)
8235#define FMC_PCR4_PWID FMC_PCR4_PWID_Msk
8236#define FMC_PCR4_PWID_0 (0x1UL << FMC_PCR4_PWID_Pos)
8237#define FMC_PCR4_PWID_1 (0x2UL << FMC_PCR4_PWID_Pos)
8238
8239#define FMC_PCR4_ECCEN_Pos (6U)
8240#define FMC_PCR4_ECCEN_Msk (0x1UL << FMC_PCR4_ECCEN_Pos)
8241#define FMC_PCR4_ECCEN FMC_PCR4_ECCEN_Msk
8242
8243#define FMC_PCR4_TCLR_Pos (9U)
8244#define FMC_PCR4_TCLR_Msk (0xFUL << FMC_PCR4_TCLR_Pos)
8245#define FMC_PCR4_TCLR FMC_PCR4_TCLR_Msk
8246#define FMC_PCR4_TCLR_0 (0x1UL << FMC_PCR4_TCLR_Pos)
8247#define FMC_PCR4_TCLR_1 (0x2UL << FMC_PCR4_TCLR_Pos)
8248#define FMC_PCR4_TCLR_2 (0x4UL << FMC_PCR4_TCLR_Pos)
8249#define FMC_PCR4_TCLR_3 (0x8UL << FMC_PCR4_TCLR_Pos)
8250
8251#define FMC_PCR4_TAR_Pos (13U)
8252#define FMC_PCR4_TAR_Msk (0xFUL << FMC_PCR4_TAR_Pos)
8253#define FMC_PCR4_TAR FMC_PCR4_TAR_Msk
8254#define FMC_PCR4_TAR_0 (0x1UL << FMC_PCR4_TAR_Pos)
8255#define FMC_PCR4_TAR_1 (0x2UL << FMC_PCR4_TAR_Pos)
8256#define FMC_PCR4_TAR_2 (0x4UL << FMC_PCR4_TAR_Pos)
8257#define FMC_PCR4_TAR_3 (0x8UL << FMC_PCR4_TAR_Pos)
8258
8259#define FMC_PCR4_ECCPS_Pos (17U)
8260#define FMC_PCR4_ECCPS_Msk (0x7UL << FMC_PCR4_ECCPS_Pos)
8261#define FMC_PCR4_ECCPS FMC_PCR4_ECCPS_Msk
8262#define FMC_PCR4_ECCPS_0 (0x1UL << FMC_PCR4_ECCPS_Pos)
8263#define FMC_PCR4_ECCPS_1 (0x2UL << FMC_PCR4_ECCPS_Pos)
8264#define FMC_PCR4_ECCPS_2 (0x4UL << FMC_PCR4_ECCPS_Pos)
8265
8266/******************* Bit definition for FMC_SR2 register *******************/
8267#define FMC_SR2_IRS_Pos (0U)
8268#define FMC_SR2_IRS_Msk (0x1UL << FMC_SR2_IRS_Pos)
8269#define FMC_SR2_IRS FMC_SR2_IRS_Msk
8270#define FMC_SR2_ILS_Pos (1U)
8271#define FMC_SR2_ILS_Msk (0x1UL << FMC_SR2_ILS_Pos)
8272#define FMC_SR2_ILS FMC_SR2_ILS_Msk
8273#define FMC_SR2_IFS_Pos (2U)
8274#define FMC_SR2_IFS_Msk (0x1UL << FMC_SR2_IFS_Pos)
8275#define FMC_SR2_IFS FMC_SR2_IFS_Msk
8276#define FMC_SR2_IREN_Pos (3U)
8277#define FMC_SR2_IREN_Msk (0x1UL << FMC_SR2_IREN_Pos)
8278#define FMC_SR2_IREN FMC_SR2_IREN_Msk
8279#define FMC_SR2_ILEN_Pos (4U)
8280#define FMC_SR2_ILEN_Msk (0x1UL << FMC_SR2_ILEN_Pos)
8281#define FMC_SR2_ILEN FMC_SR2_ILEN_Msk
8282#define FMC_SR2_IFEN_Pos (5U)
8283#define FMC_SR2_IFEN_Msk (0x1UL << FMC_SR2_IFEN_Pos)
8284#define FMC_SR2_IFEN FMC_SR2_IFEN_Msk
8285#define FMC_SR2_FEMPT_Pos (6U)
8286#define FMC_SR2_FEMPT_Msk (0x1UL << FMC_SR2_FEMPT_Pos)
8287#define FMC_SR2_FEMPT FMC_SR2_FEMPT_Msk
8288
8289/******************* Bit definition for FMC_SR3 register *******************/
8290#define FMC_SR3_IRS_Pos (0U)
8291#define FMC_SR3_IRS_Msk (0x1UL << FMC_SR3_IRS_Pos)
8292#define FMC_SR3_IRS FMC_SR3_IRS_Msk
8293#define FMC_SR3_ILS_Pos (1U)
8294#define FMC_SR3_ILS_Msk (0x1UL << FMC_SR3_ILS_Pos)
8295#define FMC_SR3_ILS FMC_SR3_ILS_Msk
8296#define FMC_SR3_IFS_Pos (2U)
8297#define FMC_SR3_IFS_Msk (0x1UL << FMC_SR3_IFS_Pos)
8298#define FMC_SR3_IFS FMC_SR3_IFS_Msk
8299#define FMC_SR3_IREN_Pos (3U)
8300#define FMC_SR3_IREN_Msk (0x1UL << FMC_SR3_IREN_Pos)
8301#define FMC_SR3_IREN FMC_SR3_IREN_Msk
8302#define FMC_SR3_ILEN_Pos (4U)
8303#define FMC_SR3_ILEN_Msk (0x1UL << FMC_SR3_ILEN_Pos)
8304#define FMC_SR3_ILEN FMC_SR3_ILEN_Msk
8305#define FMC_SR3_IFEN_Pos (5U)
8306#define FMC_SR3_IFEN_Msk (0x1UL << FMC_SR3_IFEN_Pos)
8307#define FMC_SR3_IFEN FMC_SR3_IFEN_Msk
8308#define FMC_SR3_FEMPT_Pos (6U)
8309#define FMC_SR3_FEMPT_Msk (0x1UL << FMC_SR3_FEMPT_Pos)
8310#define FMC_SR3_FEMPT FMC_SR3_FEMPT_Msk
8311
8312/******************* Bit definition for FMC_SR4 register *******************/
8313#define FMC_SR4_IRS_Pos (0U)
8314#define FMC_SR4_IRS_Msk (0x1UL << FMC_SR4_IRS_Pos)
8315#define FMC_SR4_IRS FMC_SR4_IRS_Msk
8316#define FMC_SR4_ILS_Pos (1U)
8317#define FMC_SR4_ILS_Msk (0x1UL << FMC_SR4_ILS_Pos)
8318#define FMC_SR4_ILS FMC_SR4_ILS_Msk
8319#define FMC_SR4_IFS_Pos (2U)
8320#define FMC_SR4_IFS_Msk (0x1UL << FMC_SR4_IFS_Pos)
8321#define FMC_SR4_IFS FMC_SR4_IFS_Msk
8322#define FMC_SR4_IREN_Pos (3U)
8323#define FMC_SR4_IREN_Msk (0x1UL << FMC_SR4_IREN_Pos)
8324#define FMC_SR4_IREN FMC_SR4_IREN_Msk
8325#define FMC_SR4_ILEN_Pos (4U)
8326#define FMC_SR4_ILEN_Msk (0x1UL << FMC_SR4_ILEN_Pos)
8327#define FMC_SR4_ILEN FMC_SR4_ILEN_Msk
8328#define FMC_SR4_IFEN_Pos (5U)
8329#define FMC_SR4_IFEN_Msk (0x1UL << FMC_SR4_IFEN_Pos)
8330#define FMC_SR4_IFEN FMC_SR4_IFEN_Msk
8331#define FMC_SR4_FEMPT_Pos (6U)
8332#define FMC_SR4_FEMPT_Msk (0x1UL << FMC_SR4_FEMPT_Pos)
8333#define FMC_SR4_FEMPT FMC_SR4_FEMPT_Msk
8334
8335/****************** Bit definition for FMC_PMEM2 register ******************/
8336#define FMC_PMEM2_MEMSET2_Pos (0U)
8337#define FMC_PMEM2_MEMSET2_Msk (0xFFUL << FMC_PMEM2_MEMSET2_Pos)
8338#define FMC_PMEM2_MEMSET2 FMC_PMEM2_MEMSET2_Msk
8339#define FMC_PMEM2_MEMSET2_0 (0x01UL << FMC_PMEM2_MEMSET2_Pos)
8340#define FMC_PMEM2_MEMSET2_1 (0x02UL << FMC_PMEM2_MEMSET2_Pos)
8341#define FMC_PMEM2_MEMSET2_2 (0x04UL << FMC_PMEM2_MEMSET2_Pos)
8342#define FMC_PMEM2_MEMSET2_3 (0x08UL << FMC_PMEM2_MEMSET2_Pos)
8343#define FMC_PMEM2_MEMSET2_4 (0x10UL << FMC_PMEM2_MEMSET2_Pos)
8344#define FMC_PMEM2_MEMSET2_5 (0x20UL << FMC_PMEM2_MEMSET2_Pos)
8345#define FMC_PMEM2_MEMSET2_6 (0x40UL << FMC_PMEM2_MEMSET2_Pos)
8346#define FMC_PMEM2_MEMSET2_7 (0x80UL << FMC_PMEM2_MEMSET2_Pos)
8347
8348#define FMC_PMEM2_MEMWAIT2_Pos (8U)
8349#define FMC_PMEM2_MEMWAIT2_Msk (0xFFUL << FMC_PMEM2_MEMWAIT2_Pos)
8350#define FMC_PMEM2_MEMWAIT2 FMC_PMEM2_MEMWAIT2_Msk
8351#define FMC_PMEM2_MEMWAIT2_0 (0x01UL << FMC_PMEM2_MEMWAIT2_Pos)
8352#define FMC_PMEM2_MEMWAIT2_1 (0x02UL << FMC_PMEM2_MEMWAIT2_Pos)
8353#define FMC_PMEM2_MEMWAIT2_2 (0x04UL << FMC_PMEM2_MEMWAIT2_Pos)
8354#define FMC_PMEM2_MEMWAIT2_3 (0x08UL << FMC_PMEM2_MEMWAIT2_Pos)
8355#define FMC_PMEM2_MEMWAIT2_4 (0x10UL << FMC_PMEM2_MEMWAIT2_Pos)
8356#define FMC_PMEM2_MEMWAIT2_5 (0x20UL << FMC_PMEM2_MEMWAIT2_Pos)
8357#define FMC_PMEM2_MEMWAIT2_6 (0x40UL << FMC_PMEM2_MEMWAIT2_Pos)
8358#define FMC_PMEM2_MEMWAIT2_7 (0x80UL << FMC_PMEM2_MEMWAIT2_Pos)
8359
8360#define FMC_PMEM2_MEMHOLD2_Pos (16U)
8361#define FMC_PMEM2_MEMHOLD2_Msk (0xFFUL << FMC_PMEM2_MEMHOLD2_Pos)
8362#define FMC_PMEM2_MEMHOLD2 FMC_PMEM2_MEMHOLD2_Msk
8363#define FMC_PMEM2_MEMHOLD2_0 (0x01UL << FMC_PMEM2_MEMHOLD2_Pos)
8364#define FMC_PMEM2_MEMHOLD2_1 (0x02UL << FMC_PMEM2_MEMHOLD2_Pos)
8365#define FMC_PMEM2_MEMHOLD2_2 (0x04UL << FMC_PMEM2_MEMHOLD2_Pos)
8366#define FMC_PMEM2_MEMHOLD2_3 (0x08UL << FMC_PMEM2_MEMHOLD2_Pos)
8367#define FMC_PMEM2_MEMHOLD2_4 (0x10UL << FMC_PMEM2_MEMHOLD2_Pos)
8368#define FMC_PMEM2_MEMHOLD2_5 (0x20UL << FMC_PMEM2_MEMHOLD2_Pos)
8369#define FMC_PMEM2_MEMHOLD2_6 (0x40UL << FMC_PMEM2_MEMHOLD2_Pos)
8370#define FMC_PMEM2_MEMHOLD2_7 (0x80UL << FMC_PMEM2_MEMHOLD2_Pos)
8371
8372#define FMC_PMEM2_MEMHIZ2_Pos (24U)
8373#define FMC_PMEM2_MEMHIZ2_Msk (0xFFUL << FMC_PMEM2_MEMHIZ2_Pos)
8374#define FMC_PMEM2_MEMHIZ2 FMC_PMEM2_MEMHIZ2_Msk
8375#define FMC_PMEM2_MEMHIZ2_0 (0x01UL << FMC_PMEM2_MEMHIZ2_Pos)
8376#define FMC_PMEM2_MEMHIZ2_1 (0x02UL << FMC_PMEM2_MEMHIZ2_Pos)
8377#define FMC_PMEM2_MEMHIZ2_2 (0x04UL << FMC_PMEM2_MEMHIZ2_Pos)
8378#define FMC_PMEM2_MEMHIZ2_3 (0x08UL << FMC_PMEM2_MEMHIZ2_Pos)
8379#define FMC_PMEM2_MEMHIZ2_4 (0x10UL << FMC_PMEM2_MEMHIZ2_Pos)
8380#define FMC_PMEM2_MEMHIZ2_5 (0x20UL << FMC_PMEM2_MEMHIZ2_Pos)
8381#define FMC_PMEM2_MEMHIZ2_6 (0x40UL << FMC_PMEM2_MEMHIZ2_Pos)
8382#define FMC_PMEM2_MEMHIZ2_7 (0x80UL << FMC_PMEM2_MEMHIZ2_Pos)
8383
8384/****************** Bit definition for FMC_PMEM3 register ******************/
8385#define FMC_PMEM3_MEMSET3_Pos (0U)
8386#define FMC_PMEM3_MEMSET3_Msk (0xFFUL << FMC_PMEM3_MEMSET3_Pos)
8387#define FMC_PMEM3_MEMSET3 FMC_PMEM3_MEMSET3_Msk
8388#define FMC_PMEM3_MEMSET3_0 (0x01UL << FMC_PMEM3_MEMSET3_Pos)
8389#define FMC_PMEM3_MEMSET3_1 (0x02UL << FMC_PMEM3_MEMSET3_Pos)
8390#define FMC_PMEM3_MEMSET3_2 (0x04UL << FMC_PMEM3_MEMSET3_Pos)
8391#define FMC_PMEM3_MEMSET3_3 (0x08UL << FMC_PMEM3_MEMSET3_Pos)
8392#define FMC_PMEM3_MEMSET3_4 (0x10UL << FMC_PMEM3_MEMSET3_Pos)
8393#define FMC_PMEM3_MEMSET3_5 (0x20UL << FMC_PMEM3_MEMSET3_Pos)
8394#define FMC_PMEM3_MEMSET3_6 (0x40UL << FMC_PMEM3_MEMSET3_Pos)
8395#define FMC_PMEM3_MEMSET3_7 (0x80UL << FMC_PMEM3_MEMSET3_Pos)
8396
8397#define FMC_PMEM3_MEMWAIT3_Pos (8U)
8398#define FMC_PMEM3_MEMWAIT3_Msk (0xFFUL << FMC_PMEM3_MEMWAIT3_Pos)
8399#define FMC_PMEM3_MEMWAIT3 FMC_PMEM3_MEMWAIT3_Msk
8400#define FMC_PMEM3_MEMWAIT3_0 (0x01UL << FMC_PMEM3_MEMWAIT3_Pos)
8401#define FMC_PMEM3_MEMWAIT3_1 (0x02UL << FMC_PMEM3_MEMWAIT3_Pos)
8402#define FMC_PMEM3_MEMWAIT3_2 (0x04UL << FMC_PMEM3_MEMWAIT3_Pos)
8403#define FMC_PMEM3_MEMWAIT3_3 (0x08UL << FMC_PMEM3_MEMWAIT3_Pos)
8404#define FMC_PMEM3_MEMWAIT3_4 (0x10UL << FMC_PMEM3_MEMWAIT3_Pos)
8405#define FMC_PMEM3_MEMWAIT3_5 (0x20UL << FMC_PMEM3_MEMWAIT3_Pos)
8406#define FMC_PMEM3_MEMWAIT3_6 (0x40UL << FMC_PMEM3_MEMWAIT3_Pos)
8407#define FMC_PMEM3_MEMWAIT3_7 (0x80UL << FMC_PMEM3_MEMWAIT3_Pos)
8408
8409#define FMC_PMEM3_MEMHOLD3_Pos (16U)
8410#define FMC_PMEM3_MEMHOLD3_Msk (0xFFUL << FMC_PMEM3_MEMHOLD3_Pos)
8411#define FMC_PMEM3_MEMHOLD3 FMC_PMEM3_MEMHOLD3_Msk
8412#define FMC_PMEM3_MEMHOLD3_0 (0x01UL << FMC_PMEM3_MEMHOLD3_Pos)
8413#define FMC_PMEM3_MEMHOLD3_1 (0x02UL << FMC_PMEM3_MEMHOLD3_Pos)
8414#define FMC_PMEM3_MEMHOLD3_2 (0x04UL << FMC_PMEM3_MEMHOLD3_Pos)
8415#define FMC_PMEM3_MEMHOLD3_3 (0x08UL << FMC_PMEM3_MEMHOLD3_Pos)
8416#define FMC_PMEM3_MEMHOLD3_4 (0x10UL << FMC_PMEM3_MEMHOLD3_Pos)
8417#define FMC_PMEM3_MEMHOLD3_5 (0x20UL << FMC_PMEM3_MEMHOLD3_Pos)
8418#define FMC_PMEM3_MEMHOLD3_6 (0x40UL << FMC_PMEM3_MEMHOLD3_Pos)
8419#define FMC_PMEM3_MEMHOLD3_7 (0x80UL << FMC_PMEM3_MEMHOLD3_Pos)
8420
8421#define FMC_PMEM3_MEMHIZ3_Pos (24U)
8422#define FMC_PMEM3_MEMHIZ3_Msk (0xFFUL << FMC_PMEM3_MEMHIZ3_Pos)
8423#define FMC_PMEM3_MEMHIZ3 FMC_PMEM3_MEMHIZ3_Msk
8424#define FMC_PMEM3_MEMHIZ3_0 (0x01UL << FMC_PMEM3_MEMHIZ3_Pos)
8425#define FMC_PMEM3_MEMHIZ3_1 (0x02UL << FMC_PMEM3_MEMHIZ3_Pos)
8426#define FMC_PMEM3_MEMHIZ3_2 (0x04UL << FMC_PMEM3_MEMHIZ3_Pos)
8427#define FMC_PMEM3_MEMHIZ3_3 (0x08UL << FMC_PMEM3_MEMHIZ3_Pos)
8428#define FMC_PMEM3_MEMHIZ3_4 (0x10UL << FMC_PMEM3_MEMHIZ3_Pos)
8429#define FMC_PMEM3_MEMHIZ3_5 (0x20UL << FMC_PMEM3_MEMHIZ3_Pos)
8430#define FMC_PMEM3_MEMHIZ3_6 (0x40UL << FMC_PMEM3_MEMHIZ3_Pos)
8431#define FMC_PMEM3_MEMHIZ3_7 (0x80UL << FMC_PMEM3_MEMHIZ3_Pos)
8432
8433/****************** Bit definition for FMC_PMEM4 register ******************/
8434#define FMC_PMEM4_MEMSET4_Pos (0U)
8435#define FMC_PMEM4_MEMSET4_Msk (0xFFUL << FMC_PMEM4_MEMSET4_Pos)
8436#define FMC_PMEM4_MEMSET4 FMC_PMEM4_MEMSET4_Msk
8437#define FMC_PMEM4_MEMSET4_0 (0x01UL << FMC_PMEM4_MEMSET4_Pos)
8438#define FMC_PMEM4_MEMSET4_1 (0x02UL << FMC_PMEM4_MEMSET4_Pos)
8439#define FMC_PMEM4_MEMSET4_2 (0x04UL << FMC_PMEM4_MEMSET4_Pos)
8440#define FMC_PMEM4_MEMSET4_3 (0x08UL << FMC_PMEM4_MEMSET4_Pos)
8441#define FMC_PMEM4_MEMSET4_4 (0x10UL << FMC_PMEM4_MEMSET4_Pos)
8442#define FMC_PMEM4_MEMSET4_5 (0x20UL << FMC_PMEM4_MEMSET4_Pos)
8443#define FMC_PMEM4_MEMSET4_6 (0x40UL << FMC_PMEM4_MEMSET4_Pos)
8444#define FMC_PMEM4_MEMSET4_7 (0x80UL << FMC_PMEM4_MEMSET4_Pos)
8445
8446#define FMC_PMEM4_MEMWAIT4_Pos (8U)
8447#define FMC_PMEM4_MEMWAIT4_Msk (0xFFUL << FMC_PMEM4_MEMWAIT4_Pos)
8448#define FMC_PMEM4_MEMWAIT4 FMC_PMEM4_MEMWAIT4_Msk
8449#define FMC_PMEM4_MEMWAIT4_0 (0x01UL << FMC_PMEM4_MEMWAIT4_Pos)
8450#define FMC_PMEM4_MEMWAIT4_1 (0x02UL << FMC_PMEM4_MEMWAIT4_Pos)
8451#define FMC_PMEM4_MEMWAIT4_2 (0x04UL << FMC_PMEM4_MEMWAIT4_Pos)
8452#define FMC_PMEM4_MEMWAIT4_3 (0x08UL << FMC_PMEM4_MEMWAIT4_Pos)
8453#define FMC_PMEM4_MEMWAIT4_4 (0x10UL << FMC_PMEM4_MEMWAIT4_Pos)
8454#define FMC_PMEM4_MEMWAIT4_5 (0x20UL << FMC_PMEM4_MEMWAIT4_Pos)
8455#define FMC_PMEM4_MEMWAIT4_6 (0x40UL << FMC_PMEM4_MEMWAIT4_Pos)
8456#define FMC_PMEM4_MEMWAIT4_7 (0x80UL << FMC_PMEM4_MEMWAIT4_Pos)
8457
8458#define FMC_PMEM4_MEMHOLD4_Pos (16U)
8459#define FMC_PMEM4_MEMHOLD4_Msk (0xFFUL << FMC_PMEM4_MEMHOLD4_Pos)
8460#define FMC_PMEM4_MEMHOLD4 FMC_PMEM4_MEMHOLD4_Msk
8461#define FMC_PMEM4_MEMHOLD4_0 (0x01UL << FMC_PMEM4_MEMHOLD4_Pos)
8462#define FMC_PMEM4_MEMHOLD4_1 (0x02UL << FMC_PMEM4_MEMHOLD4_Pos)
8463#define FMC_PMEM4_MEMHOLD4_2 (0x04UL << FMC_PMEM4_MEMHOLD4_Pos)
8464#define FMC_PMEM4_MEMHOLD4_3 (0x08UL << FMC_PMEM4_MEMHOLD4_Pos)
8465#define FMC_PMEM4_MEMHOLD4_4 (0x10UL << FMC_PMEM4_MEMHOLD4_Pos)
8466#define FMC_PMEM4_MEMHOLD4_5 (0x20UL << FMC_PMEM4_MEMHOLD4_Pos)
8467#define FMC_PMEM4_MEMHOLD4_6 (0x40UL << FMC_PMEM4_MEMHOLD4_Pos)
8468#define FMC_PMEM4_MEMHOLD4_7 (0x80UL << FMC_PMEM4_MEMHOLD4_Pos)
8469
8470#define FMC_PMEM4_MEMHIZ4_Pos (24U)
8471#define FMC_PMEM4_MEMHIZ4_Msk (0xFFUL << FMC_PMEM4_MEMHIZ4_Pos)
8472#define FMC_PMEM4_MEMHIZ4 FMC_PMEM4_MEMHIZ4_Msk
8473#define FMC_PMEM4_MEMHIZ4_0 (0x01UL << FMC_PMEM4_MEMHIZ4_Pos)
8474#define FMC_PMEM4_MEMHIZ4_1 (0x02UL << FMC_PMEM4_MEMHIZ4_Pos)
8475#define FMC_PMEM4_MEMHIZ4_2 (0x04UL << FMC_PMEM4_MEMHIZ4_Pos)
8476#define FMC_PMEM4_MEMHIZ4_3 (0x08UL << FMC_PMEM4_MEMHIZ4_Pos)
8477#define FMC_PMEM4_MEMHIZ4_4 (0x10UL << FMC_PMEM4_MEMHIZ4_Pos)
8478#define FMC_PMEM4_MEMHIZ4_5 (0x20UL << FMC_PMEM4_MEMHIZ4_Pos)
8479#define FMC_PMEM4_MEMHIZ4_6 (0x40UL << FMC_PMEM4_MEMHIZ4_Pos)
8480#define FMC_PMEM4_MEMHIZ4_7 (0x80UL << FMC_PMEM4_MEMHIZ4_Pos)
8481
8482/****************** Bit definition for FMC_PATT2 register ******************/
8483#define FMC_PATT2_ATTSET2_Pos (0U)
8484#define FMC_PATT2_ATTSET2_Msk (0xFFUL << FMC_PATT2_ATTSET2_Pos)
8485#define FMC_PATT2_ATTSET2 FMC_PATT2_ATTSET2_Msk
8486#define FMC_PATT2_ATTSET2_0 (0x01UL << FMC_PATT2_ATTSET2_Pos)
8487#define FMC_PATT2_ATTSET2_1 (0x02UL << FMC_PATT2_ATTSET2_Pos)
8488#define FMC_PATT2_ATTSET2_2 (0x04UL << FMC_PATT2_ATTSET2_Pos)
8489#define FMC_PATT2_ATTSET2_3 (0x08UL << FMC_PATT2_ATTSET2_Pos)
8490#define FMC_PATT2_ATTSET2_4 (0x10UL << FMC_PATT2_ATTSET2_Pos)
8491#define FMC_PATT2_ATTSET2_5 (0x20UL << FMC_PATT2_ATTSET2_Pos)
8492#define FMC_PATT2_ATTSET2_6 (0x40UL << FMC_PATT2_ATTSET2_Pos)
8493#define FMC_PATT2_ATTSET2_7 (0x80UL << FMC_PATT2_ATTSET2_Pos)
8494
8495#define FMC_PATT2_ATTWAIT2_Pos (8U)
8496#define FMC_PATT2_ATTWAIT2_Msk (0xFFUL << FMC_PATT2_ATTWAIT2_Pos)
8497#define FMC_PATT2_ATTWAIT2 FMC_PATT2_ATTWAIT2_Msk
8498#define FMC_PATT2_ATTWAIT2_0 (0x01UL << FMC_PATT2_ATTWAIT2_Pos)
8499#define FMC_PATT2_ATTWAIT2_1 (0x02UL << FMC_PATT2_ATTWAIT2_Pos)
8500#define FMC_PATT2_ATTWAIT2_2 (0x04UL << FMC_PATT2_ATTWAIT2_Pos)
8501#define FMC_PATT2_ATTWAIT2_3 (0x08UL << FMC_PATT2_ATTWAIT2_Pos)
8502#define FMC_PATT2_ATTWAIT2_4 (0x10UL << FMC_PATT2_ATTWAIT2_Pos)
8503#define FMC_PATT2_ATTWAIT2_5 (0x20UL << FMC_PATT2_ATTWAIT2_Pos)
8504#define FMC_PATT2_ATTWAIT2_6 (0x40UL << FMC_PATT2_ATTWAIT2_Pos)
8505#define FMC_PATT2_ATTWAIT2_7 (0x80UL << FMC_PATT2_ATTWAIT2_Pos)
8506
8507#define FMC_PATT2_ATTHOLD2_Pos (16U)
8508#define FMC_PATT2_ATTHOLD2_Msk (0xFFUL << FMC_PATT2_ATTHOLD2_Pos)
8509#define FMC_PATT2_ATTHOLD2 FMC_PATT2_ATTHOLD2_Msk
8510#define FMC_PATT2_ATTHOLD2_0 (0x01UL << FMC_PATT2_ATTHOLD2_Pos)
8511#define FMC_PATT2_ATTHOLD2_1 (0x02UL << FMC_PATT2_ATTHOLD2_Pos)
8512#define FMC_PATT2_ATTHOLD2_2 (0x04UL << FMC_PATT2_ATTHOLD2_Pos)
8513#define FMC_PATT2_ATTHOLD2_3 (0x08UL << FMC_PATT2_ATTHOLD2_Pos)
8514#define FMC_PATT2_ATTHOLD2_4 (0x10UL << FMC_PATT2_ATTHOLD2_Pos)
8515#define FMC_PATT2_ATTHOLD2_5 (0x20UL << FMC_PATT2_ATTHOLD2_Pos)
8516#define FMC_PATT2_ATTHOLD2_6 (0x40UL << FMC_PATT2_ATTHOLD2_Pos)
8517#define FMC_PATT2_ATTHOLD2_7 (0x80UL << FMC_PATT2_ATTHOLD2_Pos)
8518
8519#define FMC_PATT2_ATTHIZ2_Pos (24U)
8520#define FMC_PATT2_ATTHIZ2_Msk (0xFFUL << FMC_PATT2_ATTHIZ2_Pos)
8521#define FMC_PATT2_ATTHIZ2 FMC_PATT2_ATTHIZ2_Msk
8522#define FMC_PATT2_ATTHIZ2_0 (0x01UL << FMC_PATT2_ATTHIZ2_Pos)
8523#define FMC_PATT2_ATTHIZ2_1 (0x02UL << FMC_PATT2_ATTHIZ2_Pos)
8524#define FMC_PATT2_ATTHIZ2_2 (0x04UL << FMC_PATT2_ATTHIZ2_Pos)
8525#define FMC_PATT2_ATTHIZ2_3 (0x08UL << FMC_PATT2_ATTHIZ2_Pos)
8526#define FMC_PATT2_ATTHIZ2_4 (0x10UL << FMC_PATT2_ATTHIZ2_Pos)
8527#define FMC_PATT2_ATTHIZ2_5 (0x20UL << FMC_PATT2_ATTHIZ2_Pos)
8528#define FMC_PATT2_ATTHIZ2_6 (0x40UL << FMC_PATT2_ATTHIZ2_Pos)
8529#define FMC_PATT2_ATTHIZ2_7 (0x80UL << FMC_PATT2_ATTHIZ2_Pos)
8530
8531/****************** Bit definition for FMC_PATT3 register ******************/
8532#define FMC_PATT3_ATTSET3_Pos (0U)
8533#define FMC_PATT3_ATTSET3_Msk (0xFFUL << FMC_PATT3_ATTSET3_Pos)
8534#define FMC_PATT3_ATTSET3 FMC_PATT3_ATTSET3_Msk
8535#define FMC_PATT3_ATTSET3_0 (0x01UL << FMC_PATT3_ATTSET3_Pos)
8536#define FMC_PATT3_ATTSET3_1 (0x02UL << FMC_PATT3_ATTSET3_Pos)
8537#define FMC_PATT3_ATTSET3_2 (0x04UL << FMC_PATT3_ATTSET3_Pos)
8538#define FMC_PATT3_ATTSET3_3 (0x08UL << FMC_PATT3_ATTSET3_Pos)
8539#define FMC_PATT3_ATTSET3_4 (0x10UL << FMC_PATT3_ATTSET3_Pos)
8540#define FMC_PATT3_ATTSET3_5 (0x20UL << FMC_PATT3_ATTSET3_Pos)
8541#define FMC_PATT3_ATTSET3_6 (0x40UL << FMC_PATT3_ATTSET3_Pos)
8542#define FMC_PATT3_ATTSET3_7 (0x80UL << FMC_PATT3_ATTSET3_Pos)
8543
8544#define FMC_PATT3_ATTWAIT3_Pos (8U)
8545#define FMC_PATT3_ATTWAIT3_Msk (0xFFUL << FMC_PATT3_ATTWAIT3_Pos)
8546#define FMC_PATT3_ATTWAIT3 FMC_PATT3_ATTWAIT3_Msk
8547#define FMC_PATT3_ATTWAIT3_0 (0x01UL << FMC_PATT3_ATTWAIT3_Pos)
8548#define FMC_PATT3_ATTWAIT3_1 (0x02UL << FMC_PATT3_ATTWAIT3_Pos)
8549#define FMC_PATT3_ATTWAIT3_2 (0x04UL << FMC_PATT3_ATTWAIT3_Pos)
8550#define FMC_PATT3_ATTWAIT3_3 (0x08UL << FMC_PATT3_ATTWAIT3_Pos)
8551#define FMC_PATT3_ATTWAIT3_4 (0x10UL << FMC_PATT3_ATTWAIT3_Pos)
8552#define FMC_PATT3_ATTWAIT3_5 (0x20UL << FMC_PATT3_ATTWAIT3_Pos)
8553#define FMC_PATT3_ATTWAIT3_6 (0x40UL << FMC_PATT3_ATTWAIT3_Pos)
8554#define FMC_PATT3_ATTWAIT3_7 (0x80UL << FMC_PATT3_ATTWAIT3_Pos)
8555
8556#define FMC_PATT3_ATTHOLD3_Pos (16U)
8557#define FMC_PATT3_ATTHOLD3_Msk (0xFFUL << FMC_PATT3_ATTHOLD3_Pos)
8558#define FMC_PATT3_ATTHOLD3 FMC_PATT3_ATTHOLD3_Msk
8559#define FMC_PATT3_ATTHOLD3_0 (0x01UL << FMC_PATT3_ATTHOLD3_Pos)
8560#define FMC_PATT3_ATTHOLD3_1 (0x02UL << FMC_PATT3_ATTHOLD3_Pos)
8561#define FMC_PATT3_ATTHOLD3_2 (0x04UL << FMC_PATT3_ATTHOLD3_Pos)
8562#define FMC_PATT3_ATTHOLD3_3 (0x08UL << FMC_PATT3_ATTHOLD3_Pos)
8563#define FMC_PATT3_ATTHOLD3_4 (0x10UL << FMC_PATT3_ATTHOLD3_Pos)
8564#define FMC_PATT3_ATTHOLD3_5 (0x20UL << FMC_PATT3_ATTHOLD3_Pos)
8565#define FMC_PATT3_ATTHOLD3_6 (0x40UL << FMC_PATT3_ATTHOLD3_Pos)
8566#define FMC_PATT3_ATTHOLD3_7 (0x80UL << FMC_PATT3_ATTHOLD3_Pos)
8567
8568#define FMC_PATT3_ATTHIZ3_Pos (24U)
8569#define FMC_PATT3_ATTHIZ3_Msk (0xFFUL << FMC_PATT3_ATTHIZ3_Pos)
8570#define FMC_PATT3_ATTHIZ3 FMC_PATT3_ATTHIZ3_Msk
8571#define FMC_PATT3_ATTHIZ3_0 (0x01UL << FMC_PATT3_ATTHIZ3_Pos)
8572#define FMC_PATT3_ATTHIZ3_1 (0x02UL << FMC_PATT3_ATTHIZ3_Pos)
8573#define FMC_PATT3_ATTHIZ3_2 (0x04UL << FMC_PATT3_ATTHIZ3_Pos)
8574#define FMC_PATT3_ATTHIZ3_3 (0x08UL << FMC_PATT3_ATTHIZ3_Pos)
8575#define FMC_PATT3_ATTHIZ3_4 (0x10UL << FMC_PATT3_ATTHIZ3_Pos)
8576#define FMC_PATT3_ATTHIZ3_5 (0x20UL << FMC_PATT3_ATTHIZ3_Pos)
8577#define FMC_PATT3_ATTHIZ3_6 (0x40UL << FMC_PATT3_ATTHIZ3_Pos)
8578#define FMC_PATT3_ATTHIZ3_7 (0x80UL << FMC_PATT3_ATTHIZ3_Pos)
8579
8580/****************** Bit definition for FMC_PATT4 register ******************/
8581#define FMC_PATT4_ATTSET4_Pos (0U)
8582#define FMC_PATT4_ATTSET4_Msk (0xFFUL << FMC_PATT4_ATTSET4_Pos)
8583#define FMC_PATT4_ATTSET4 FMC_PATT4_ATTSET4_Msk
8584#define FMC_PATT4_ATTSET4_0 (0x01UL << FMC_PATT4_ATTSET4_Pos)
8585#define FMC_PATT4_ATTSET4_1 (0x02UL << FMC_PATT4_ATTSET4_Pos)
8586#define FMC_PATT4_ATTSET4_2 (0x04UL << FMC_PATT4_ATTSET4_Pos)
8587#define FMC_PATT4_ATTSET4_3 (0x08UL << FMC_PATT4_ATTSET4_Pos)
8588#define FMC_PATT4_ATTSET4_4 (0x10UL << FMC_PATT4_ATTSET4_Pos)
8589#define FMC_PATT4_ATTSET4_5 (0x20UL << FMC_PATT4_ATTSET4_Pos)
8590#define FMC_PATT4_ATTSET4_6 (0x40UL << FMC_PATT4_ATTSET4_Pos)
8591#define FMC_PATT4_ATTSET4_7 (0x80UL << FMC_PATT4_ATTSET4_Pos)
8592
8593#define FMC_PATT4_ATTWAIT4_Pos (8U)
8594#define FMC_PATT4_ATTWAIT4_Msk (0xFFUL << FMC_PATT4_ATTWAIT4_Pos)
8595#define FMC_PATT4_ATTWAIT4 FMC_PATT4_ATTWAIT4_Msk
8596#define FMC_PATT4_ATTWAIT4_0 (0x01UL << FMC_PATT4_ATTWAIT4_Pos)
8597#define FMC_PATT4_ATTWAIT4_1 (0x02UL << FMC_PATT4_ATTWAIT4_Pos)
8598#define FMC_PATT4_ATTWAIT4_2 (0x04UL << FMC_PATT4_ATTWAIT4_Pos)
8599#define FMC_PATT4_ATTWAIT4_3 (0x08UL << FMC_PATT4_ATTWAIT4_Pos)
8600#define FMC_PATT4_ATTWAIT4_4 (0x10UL << FMC_PATT4_ATTWAIT4_Pos)
8601#define FMC_PATT4_ATTWAIT4_5 (0x20UL << FMC_PATT4_ATTWAIT4_Pos)
8602#define FMC_PATT4_ATTWAIT4_6 (0x40UL << FMC_PATT4_ATTWAIT4_Pos)
8603#define FMC_PATT4_ATTWAIT4_7 (0x80UL << FMC_PATT4_ATTWAIT4_Pos)
8604
8605#define FMC_PATT4_ATTHOLD4_Pos (16U)
8606#define FMC_PATT4_ATTHOLD4_Msk (0xFFUL << FMC_PATT4_ATTHOLD4_Pos)
8607#define FMC_PATT4_ATTHOLD4 FMC_PATT4_ATTHOLD4_Msk
8608#define FMC_PATT4_ATTHOLD4_0 (0x01UL << FMC_PATT4_ATTHOLD4_Pos)
8609#define FMC_PATT4_ATTHOLD4_1 (0x02UL << FMC_PATT4_ATTHOLD4_Pos)
8610#define FMC_PATT4_ATTHOLD4_2 (0x04UL << FMC_PATT4_ATTHOLD4_Pos)
8611#define FMC_PATT4_ATTHOLD4_3 (0x08UL << FMC_PATT4_ATTHOLD4_Pos)
8612#define FMC_PATT4_ATTHOLD4_4 (0x10UL << FMC_PATT4_ATTHOLD4_Pos)
8613#define FMC_PATT4_ATTHOLD4_5 (0x20UL << FMC_PATT4_ATTHOLD4_Pos)
8614#define FMC_PATT4_ATTHOLD4_6 (0x40UL << FMC_PATT4_ATTHOLD4_Pos)
8615#define FMC_PATT4_ATTHOLD4_7 (0x80UL << FMC_PATT4_ATTHOLD4_Pos)
8616
8617#define FMC_PATT4_ATTHIZ4_Pos (24U)
8618#define FMC_PATT4_ATTHIZ4_Msk (0xFFUL << FMC_PATT4_ATTHIZ4_Pos)
8619#define FMC_PATT4_ATTHIZ4 FMC_PATT4_ATTHIZ4_Msk
8620#define FMC_PATT4_ATTHIZ4_0 (0x01UL << FMC_PATT4_ATTHIZ4_Pos)
8621#define FMC_PATT4_ATTHIZ4_1 (0x02UL << FMC_PATT4_ATTHIZ4_Pos)
8622#define FMC_PATT4_ATTHIZ4_2 (0x04UL << FMC_PATT4_ATTHIZ4_Pos)
8623#define FMC_PATT4_ATTHIZ4_3 (0x08UL << FMC_PATT4_ATTHIZ4_Pos)
8624#define FMC_PATT4_ATTHIZ4_4 (0x10UL << FMC_PATT4_ATTHIZ4_Pos)
8625#define FMC_PATT4_ATTHIZ4_5 (0x20UL << FMC_PATT4_ATTHIZ4_Pos)
8626#define FMC_PATT4_ATTHIZ4_6 (0x40UL << FMC_PATT4_ATTHIZ4_Pos)
8627#define FMC_PATT4_ATTHIZ4_7 (0x80UL << FMC_PATT4_ATTHIZ4_Pos)
8628
8629/****************** Bit definition for FMC_PIO4 register *******************/
8630#define FMC_PIO4_IOSET4_Pos (0U)
8631#define FMC_PIO4_IOSET4_Msk (0xFFUL << FMC_PIO4_IOSET4_Pos)
8632#define FMC_PIO4_IOSET4 FMC_PIO4_IOSET4_Msk
8633#define FMC_PIO4_IOSET4_0 (0x01UL << FMC_PIO4_IOSET4_Pos)
8634#define FMC_PIO4_IOSET4_1 (0x02UL << FMC_PIO4_IOSET4_Pos)
8635#define FMC_PIO4_IOSET4_2 (0x04UL << FMC_PIO4_IOSET4_Pos)
8636#define FMC_PIO4_IOSET4_3 (0x08UL << FMC_PIO4_IOSET4_Pos)
8637#define FMC_PIO4_IOSET4_4 (0x10UL << FMC_PIO4_IOSET4_Pos)
8638#define FMC_PIO4_IOSET4_5 (0x20UL << FMC_PIO4_IOSET4_Pos)
8639#define FMC_PIO4_IOSET4_6 (0x40UL << FMC_PIO4_IOSET4_Pos)
8640#define FMC_PIO4_IOSET4_7 (0x80UL << FMC_PIO4_IOSET4_Pos)
8641
8642#define FMC_PIO4_IOWAIT4_Pos (8U)
8643#define FMC_PIO4_IOWAIT4_Msk (0xFFUL << FMC_PIO4_IOWAIT4_Pos)
8644#define FMC_PIO4_IOWAIT4 FMC_PIO4_IOWAIT4_Msk
8645#define FMC_PIO4_IOWAIT4_0 (0x01UL << FMC_PIO4_IOWAIT4_Pos)
8646#define FMC_PIO4_IOWAIT4_1 (0x02UL << FMC_PIO4_IOWAIT4_Pos)
8647#define FMC_PIO4_IOWAIT4_2 (0x04UL << FMC_PIO4_IOWAIT4_Pos)
8648#define FMC_PIO4_IOWAIT4_3 (0x08UL << FMC_PIO4_IOWAIT4_Pos)
8649#define FMC_PIO4_IOWAIT4_4 (0x10UL << FMC_PIO4_IOWAIT4_Pos)
8650#define FMC_PIO4_IOWAIT4_5 (0x20UL << FMC_PIO4_IOWAIT4_Pos)
8651#define FMC_PIO4_IOWAIT4_6 (0x40UL << FMC_PIO4_IOWAIT4_Pos)
8652#define FMC_PIO4_IOWAIT4_7 (0x80UL << FMC_PIO4_IOWAIT4_Pos)
8653
8654#define FMC_PIO4_IOHOLD4_Pos (16U)
8655#define FMC_PIO4_IOHOLD4_Msk (0xFFUL << FMC_PIO4_IOHOLD4_Pos)
8656#define FMC_PIO4_IOHOLD4 FMC_PIO4_IOHOLD4_Msk
8657#define FMC_PIO4_IOHOLD4_0 (0x01UL << FMC_PIO4_IOHOLD4_Pos)
8658#define FMC_PIO4_IOHOLD4_1 (0x02UL << FMC_PIO4_IOHOLD4_Pos)
8659#define FMC_PIO4_IOHOLD4_2 (0x04UL << FMC_PIO4_IOHOLD4_Pos)
8660#define FMC_PIO4_IOHOLD4_3 (0x08UL << FMC_PIO4_IOHOLD4_Pos)
8661#define FMC_PIO4_IOHOLD4_4 (0x10UL << FMC_PIO4_IOHOLD4_Pos)
8662#define FMC_PIO4_IOHOLD4_5 (0x20UL << FMC_PIO4_IOHOLD4_Pos)
8663#define FMC_PIO4_IOHOLD4_6 (0x40UL << FMC_PIO4_IOHOLD4_Pos)
8664#define FMC_PIO4_IOHOLD4_7 (0x80UL << FMC_PIO4_IOHOLD4_Pos)
8665
8666#define FMC_PIO4_IOHIZ4_Pos (24U)
8667#define FMC_PIO4_IOHIZ4_Msk (0xFFUL << FMC_PIO4_IOHIZ4_Pos)
8668#define FMC_PIO4_IOHIZ4 FMC_PIO4_IOHIZ4_Msk
8669#define FMC_PIO4_IOHIZ4_0 (0x01UL << FMC_PIO4_IOHIZ4_Pos)
8670#define FMC_PIO4_IOHIZ4_1 (0x02UL << FMC_PIO4_IOHIZ4_Pos)
8671#define FMC_PIO4_IOHIZ4_2 (0x04UL << FMC_PIO4_IOHIZ4_Pos)
8672#define FMC_PIO4_IOHIZ4_3 (0x08UL << FMC_PIO4_IOHIZ4_Pos)
8673#define FMC_PIO4_IOHIZ4_4 (0x10UL << FMC_PIO4_IOHIZ4_Pos)
8674#define FMC_PIO4_IOHIZ4_5 (0x20UL << FMC_PIO4_IOHIZ4_Pos)
8675#define FMC_PIO4_IOHIZ4_6 (0x40UL << FMC_PIO4_IOHIZ4_Pos)
8676#define FMC_PIO4_IOHIZ4_7 (0x80UL << FMC_PIO4_IOHIZ4_Pos)
8677
8678
8679/****************** Bit definition for FMC_ECCR2 register ******************/
8680#define FMC_ECCR2_ECC2_Pos (0U)
8681#define FMC_ECCR2_ECC2_Msk (0xFFFFFFFFUL << FMC_ECCR2_ECC2_Pos)
8682#define FMC_ECCR2_ECC2 FMC_ECCR2_ECC2_Msk
8683
8684/****************** Bit definition for FMC_ECCR3 register ******************/
8685#define FMC_ECCR3_ECC3_Pos (0U)
8686#define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)
8687#define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk
8688
8689/****************** Bit definition for FMC_SDCR1 register ******************/
8690#define FMC_SDCR1_NC_Pos (0U)
8691#define FMC_SDCR1_NC_Msk (0x3UL << FMC_SDCR1_NC_Pos)
8692#define FMC_SDCR1_NC FMC_SDCR1_NC_Msk
8693#define FMC_SDCR1_NC_0 (0x1UL << FMC_SDCR1_NC_Pos)
8694#define FMC_SDCR1_NC_1 (0x2UL << FMC_SDCR1_NC_Pos)
8695
8696#define FMC_SDCR1_NR_Pos (2U)
8697#define FMC_SDCR1_NR_Msk (0x3UL << FMC_SDCR1_NR_Pos)
8698#define FMC_SDCR1_NR FMC_SDCR1_NR_Msk
8699#define FMC_SDCR1_NR_0 (0x1UL << FMC_SDCR1_NR_Pos)
8700#define FMC_SDCR1_NR_1 (0x2UL << FMC_SDCR1_NR_Pos)
8701
8702#define FMC_SDCR1_MWID_Pos (4U)
8703#define FMC_SDCR1_MWID_Msk (0x3UL << FMC_SDCR1_MWID_Pos)
8704#define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk
8705#define FMC_SDCR1_MWID_0 (0x1UL << FMC_SDCR1_MWID_Pos)
8706#define FMC_SDCR1_MWID_1 (0x2UL << FMC_SDCR1_MWID_Pos)
8707
8708#define FMC_SDCR1_NB_Pos (6U)
8709#define FMC_SDCR1_NB_Msk (0x1UL << FMC_SDCR1_NB_Pos)
8710#define FMC_SDCR1_NB FMC_SDCR1_NB_Msk
8711
8712#define FMC_SDCR1_CAS_Pos (7U)
8713#define FMC_SDCR1_CAS_Msk (0x3UL << FMC_SDCR1_CAS_Pos)
8714#define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk
8715#define FMC_SDCR1_CAS_0 (0x1UL << FMC_SDCR1_CAS_Pos)
8716#define FMC_SDCR1_CAS_1 (0x2UL << FMC_SDCR1_CAS_Pos)
8717
8718#define FMC_SDCR1_WP_Pos (9U)
8719#define FMC_SDCR1_WP_Msk (0x1UL << FMC_SDCR1_WP_Pos)
8720#define FMC_SDCR1_WP FMC_SDCR1_WP_Msk
8721
8722#define FMC_SDCR1_SDCLK_Pos (10U)
8723#define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos)
8724#define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk
8725#define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos)
8726#define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos)
8727
8728#define FMC_SDCR1_RBURST_Pos (12U)
8729#define FMC_SDCR1_RBURST_Msk (0x1UL << FMC_SDCR1_RBURST_Pos)
8730#define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk
8731
8732#define FMC_SDCR1_RPIPE_Pos (13U)
8733#define FMC_SDCR1_RPIPE_Msk (0x3UL << FMC_SDCR1_RPIPE_Pos)
8734#define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk
8735#define FMC_SDCR1_RPIPE_0 (0x1UL << FMC_SDCR1_RPIPE_Pos)
8736#define FMC_SDCR1_RPIPE_1 (0x2UL << FMC_SDCR1_RPIPE_Pos)
8737
8738/****************** Bit definition for FMC_SDCR2 register ******************/
8739#define FMC_SDCR2_NC_Pos (0U)
8740#define FMC_SDCR2_NC_Msk (0x3UL << FMC_SDCR2_NC_Pos)
8741#define FMC_SDCR2_NC FMC_SDCR2_NC_Msk
8742#define FMC_SDCR2_NC_0 (0x1UL << FMC_SDCR2_NC_Pos)
8743#define FMC_SDCR2_NC_1 (0x2UL << FMC_SDCR2_NC_Pos)
8744
8745#define FMC_SDCR2_NR_Pos (2U)
8746#define FMC_SDCR2_NR_Msk (0x3UL << FMC_SDCR2_NR_Pos)
8747#define FMC_SDCR2_NR FMC_SDCR2_NR_Msk
8748#define FMC_SDCR2_NR_0 (0x1UL << FMC_SDCR2_NR_Pos)
8749#define FMC_SDCR2_NR_1 (0x2UL << FMC_SDCR2_NR_Pos)
8750
8751#define FMC_SDCR2_MWID_Pos (4U)
8752#define FMC_SDCR2_MWID_Msk (0x3UL << FMC_SDCR2_MWID_Pos)
8753#define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk
8754#define FMC_SDCR2_MWID_0 (0x1UL << FMC_SDCR2_MWID_Pos)
8755#define FMC_SDCR2_MWID_1 (0x2UL << FMC_SDCR2_MWID_Pos)
8756
8757#define FMC_SDCR2_NB_Pos (6U)
8758#define FMC_SDCR2_NB_Msk (0x1UL << FMC_SDCR2_NB_Pos)
8759#define FMC_SDCR2_NB FMC_SDCR2_NB_Msk
8760
8761#define FMC_SDCR2_CAS_Pos (7U)
8762#define FMC_SDCR2_CAS_Msk (0x3UL << FMC_SDCR2_CAS_Pos)
8763#define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk
8764#define FMC_SDCR2_CAS_0 (0x1UL << FMC_SDCR2_CAS_Pos)
8765#define FMC_SDCR2_CAS_1 (0x2UL << FMC_SDCR2_CAS_Pos)
8766
8767#define FMC_SDCR2_WP_Pos (9U)
8768#define FMC_SDCR2_WP_Msk (0x1UL << FMC_SDCR2_WP_Pos)
8769#define FMC_SDCR2_WP FMC_SDCR2_WP_Msk
8770
8771#define FMC_SDCR2_SDCLK_Pos (10U)
8772#define FMC_SDCR2_SDCLK_Msk (0x3UL << FMC_SDCR2_SDCLK_Pos)
8773#define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk
8774#define FMC_SDCR2_SDCLK_0 (0x1UL << FMC_SDCR2_SDCLK_Pos)
8775#define FMC_SDCR2_SDCLK_1 (0x2UL << FMC_SDCR2_SDCLK_Pos)
8776
8777#define FMC_SDCR2_RBURST_Pos (12U)
8778#define FMC_SDCR2_RBURST_Msk (0x1UL << FMC_SDCR2_RBURST_Pos)
8779#define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk
8780
8781#define FMC_SDCR2_RPIPE_Pos (13U)
8782#define FMC_SDCR2_RPIPE_Msk (0x3UL << FMC_SDCR2_RPIPE_Pos)
8783#define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk
8784#define FMC_SDCR2_RPIPE_0 (0x1UL << FMC_SDCR2_RPIPE_Pos)
8785#define FMC_SDCR2_RPIPE_1 (0x2UL << FMC_SDCR2_RPIPE_Pos)
8786
8787/****************** Bit definition for FMC_SDTR1 register ******************/
8788#define FMC_SDTR1_TMRD_Pos (0U)
8789#define FMC_SDTR1_TMRD_Msk (0xFUL << FMC_SDTR1_TMRD_Pos)
8790#define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk
8791#define FMC_SDTR1_TMRD_0 (0x1UL << FMC_SDTR1_TMRD_Pos)
8792#define FMC_SDTR1_TMRD_1 (0x2UL << FMC_SDTR1_TMRD_Pos)
8793#define FMC_SDTR1_TMRD_2 (0x4UL << FMC_SDTR1_TMRD_Pos)
8794#define FMC_SDTR1_TMRD_3 (0x8UL << FMC_SDTR1_TMRD_Pos)
8795
8796#define FMC_SDTR1_TXSR_Pos (4U)
8797#define FMC_SDTR1_TXSR_Msk (0xFUL << FMC_SDTR1_TXSR_Pos)
8798#define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk
8799#define FMC_SDTR1_TXSR_0 (0x1UL << FMC_SDTR1_TXSR_Pos)
8800#define FMC_SDTR1_TXSR_1 (0x2UL << FMC_SDTR1_TXSR_Pos)
8801#define FMC_SDTR1_TXSR_2 (0x4UL << FMC_SDTR1_TXSR_Pos)
8802#define FMC_SDTR1_TXSR_3 (0x8UL << FMC_SDTR1_TXSR_Pos)
8803
8804#define FMC_SDTR1_TRAS_Pos (8U)
8805#define FMC_SDTR1_TRAS_Msk (0xFUL << FMC_SDTR1_TRAS_Pos)
8806#define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk
8807#define FMC_SDTR1_TRAS_0 (0x1UL << FMC_SDTR1_TRAS_Pos)
8808#define FMC_SDTR1_TRAS_1 (0x2UL << FMC_SDTR1_TRAS_Pos)
8809#define FMC_SDTR1_TRAS_2 (0x4UL << FMC_SDTR1_TRAS_Pos)
8810#define FMC_SDTR1_TRAS_3 (0x8UL << FMC_SDTR1_TRAS_Pos)
8811
8812#define FMC_SDTR1_TRC_Pos (12U)
8813#define FMC_SDTR1_TRC_Msk (0xFUL << FMC_SDTR1_TRC_Pos)
8814#define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk
8815#define FMC_SDTR1_TRC_0 (0x1UL << FMC_SDTR1_TRC_Pos)
8816#define FMC_SDTR1_TRC_1 (0x2UL << FMC_SDTR1_TRC_Pos)
8817#define FMC_SDTR1_TRC_2 (0x4UL << FMC_SDTR1_TRC_Pos)
8818
8819#define FMC_SDTR1_TWR_Pos (16U)
8820#define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos)
8821#define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk
8822#define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos)
8823#define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos)
8824#define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos)
8825
8826#define FMC_SDTR1_TRP_Pos (20U)
8827#define FMC_SDTR1_TRP_Msk (0xFUL << FMC_SDTR1_TRP_Pos)
8828#define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk
8829#define FMC_SDTR1_TRP_0 (0x1UL << FMC_SDTR1_TRP_Pos)
8830#define FMC_SDTR1_TRP_1 (0x2UL << FMC_SDTR1_TRP_Pos)
8831#define FMC_SDTR1_TRP_2 (0x4UL << FMC_SDTR1_TRP_Pos)
8832
8833#define FMC_SDTR1_TRCD_Pos (24U)
8834#define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos)
8835#define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk
8836#define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos)
8837#define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos)
8838#define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos)
8839
8840/****************** Bit definition for FMC_SDTR2 register ******************/
8841#define FMC_SDTR2_TMRD_Pos (0U)
8842#define FMC_SDTR2_TMRD_Msk (0xFUL << FMC_SDTR2_TMRD_Pos)
8843#define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk
8844#define FMC_SDTR2_TMRD_0 (0x1UL << FMC_SDTR2_TMRD_Pos)
8845#define FMC_SDTR2_TMRD_1 (0x2UL << FMC_SDTR2_TMRD_Pos)
8846#define FMC_SDTR2_TMRD_2 (0x4UL << FMC_SDTR2_TMRD_Pos)
8847#define FMC_SDTR2_TMRD_3 (0x8UL << FMC_SDTR2_TMRD_Pos)
8848
8849#define FMC_SDTR2_TXSR_Pos (4U)
8850#define FMC_SDTR2_TXSR_Msk (0xFUL << FMC_SDTR2_TXSR_Pos)
8851#define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk
8852#define FMC_SDTR2_TXSR_0 (0x1UL << FMC_SDTR2_TXSR_Pos)
8853#define FMC_SDTR2_TXSR_1 (0x2UL << FMC_SDTR2_TXSR_Pos)
8854#define FMC_SDTR2_TXSR_2 (0x4UL << FMC_SDTR2_TXSR_Pos)
8855#define FMC_SDTR2_TXSR_3 (0x8UL << FMC_SDTR2_TXSR_Pos)
8856
8857#define FMC_SDTR2_TRAS_Pos (8U)
8858#define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos)
8859#define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk
8860#define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos)
8861#define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos)
8862#define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos)
8863#define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos)
8864
8865#define FMC_SDTR2_TRC_Pos (12U)
8866#define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos)
8867#define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk
8868#define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos)
8869#define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos)
8870#define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos)
8871
8872#define FMC_SDTR2_TWR_Pos (16U)
8873#define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos)
8874#define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk
8875#define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos)
8876#define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos)
8877#define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos)
8878
8879#define FMC_SDTR2_TRP_Pos (20U)
8880#define FMC_SDTR2_TRP_Msk (0xFUL << FMC_SDTR2_TRP_Pos)
8881#define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk
8882#define FMC_SDTR2_TRP_0 (0x1UL << FMC_SDTR2_TRP_Pos)
8883#define FMC_SDTR2_TRP_1 (0x2UL << FMC_SDTR2_TRP_Pos)
8884#define FMC_SDTR2_TRP_2 (0x4UL << FMC_SDTR2_TRP_Pos)
8885
8886#define FMC_SDTR2_TRCD_Pos (24U)
8887#define FMC_SDTR2_TRCD_Msk (0xFUL << FMC_SDTR2_TRCD_Pos)
8888#define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk
8889#define FMC_SDTR2_TRCD_0 (0x1UL << FMC_SDTR2_TRCD_Pos)
8890#define FMC_SDTR2_TRCD_1 (0x2UL << FMC_SDTR2_TRCD_Pos)
8891#define FMC_SDTR2_TRCD_2 (0x4UL << FMC_SDTR2_TRCD_Pos)
8892
8893/****************** Bit definition for FMC_SDCMR register ******************/
8894#define FMC_SDCMR_MODE_Pos (0U)
8895#define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos)
8896#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk
8897#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos)
8898#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos)
8899#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos)
8900
8901#define FMC_SDCMR_CTB2_Pos (3U)
8902#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos)
8903#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk
8904
8905#define FMC_SDCMR_CTB1_Pos (4U)
8906#define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos)
8907#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk
8908
8909#define FMC_SDCMR_NRFS_Pos (5U)
8910#define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos)
8911#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk
8912#define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos)
8913#define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos)
8914#define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos)
8915#define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos)
8916
8917#define FMC_SDCMR_MRD_Pos (9U)
8918#define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos)
8919#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk
8920
8921/****************** Bit definition for FMC_SDRTR register ******************/
8922#define FMC_SDRTR_CRE_Pos (0U)
8923#define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos)
8924#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk
8925
8926#define FMC_SDRTR_COUNT_Pos (1U)
8927#define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos)
8928#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk
8929
8930#define FMC_SDRTR_REIE_Pos (14U)
8931#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos)
8932#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk
8933
8934/****************** Bit definition for FMC_SDSR register ******************/
8935#define FMC_SDSR_RE_Pos (0U)
8936#define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos)
8937#define FMC_SDSR_RE FMC_SDSR_RE_Msk
8938
8939#define FMC_SDSR_MODES1_Pos (1U)
8940#define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos)
8941#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk
8942#define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos)
8943#define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos)
8944
8945#define FMC_SDSR_MODES2_Pos (3U)
8946#define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos)
8947#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk
8948#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos)
8949#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos)
8950#define FMC_SDSR_BUSY_Pos (5U)
8951#define FMC_SDSR_BUSY_Msk (0x1UL << FMC_SDSR_BUSY_Pos)
8952#define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk
8953
8954/******************************************************************************/
8955/* */
8956/* General Purpose I/O */
8957/* */
8958/******************************************************************************/
8959/****************** Bits definition for GPIO_MODER register *****************/
8960#define GPIO_MODER_MODER0_Pos (0U)
8961#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
8962#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
8963#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
8964#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
8965#define GPIO_MODER_MODER1_Pos (2U)
8966#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
8967#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
8968#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
8969#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
8970#define GPIO_MODER_MODER2_Pos (4U)
8971#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
8972#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
8973#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
8974#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
8975#define GPIO_MODER_MODER3_Pos (6U)
8976#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
8977#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
8978#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
8979#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
8980#define GPIO_MODER_MODER4_Pos (8U)
8981#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
8982#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
8983#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
8984#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
8985#define GPIO_MODER_MODER5_Pos (10U)
8986#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
8987#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
8988#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
8989#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
8990#define GPIO_MODER_MODER6_Pos (12U)
8991#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
8992#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
8993#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
8994#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
8995#define GPIO_MODER_MODER7_Pos (14U)
8996#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
8997#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
8998#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
8999#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
9000#define GPIO_MODER_MODER8_Pos (16U)
9001#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
9002#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
9003#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
9004#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
9005#define GPIO_MODER_MODER9_Pos (18U)
9006#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
9007#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
9008#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
9009#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
9010#define GPIO_MODER_MODER10_Pos (20U)
9011#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
9012#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
9013#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
9014#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
9015#define GPIO_MODER_MODER11_Pos (22U)
9016#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
9017#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
9018#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
9019#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
9020#define GPIO_MODER_MODER12_Pos (24U)
9021#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
9022#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
9023#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
9024#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
9025#define GPIO_MODER_MODER13_Pos (26U)
9026#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
9027#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
9028#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
9029#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
9030#define GPIO_MODER_MODER14_Pos (28U)
9031#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
9032#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
9033#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
9034#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
9035#define GPIO_MODER_MODER15_Pos (30U)
9036#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
9037#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
9038#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
9039#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
9040
9041/* Legacy defines */
9042#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos
9043#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk
9044#define GPIO_MODER_MODE0 GPIO_MODER_MODER0
9045#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0
9046#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1
9047#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos
9048#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk
9049#define GPIO_MODER_MODE1 GPIO_MODER_MODER1
9050#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
9051#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
9052#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
9053#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
9054#define GPIO_MODER_MODE2 GPIO_MODER_MODER2
9055#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
9056#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1
9057#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos
9058#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk
9059#define GPIO_MODER_MODE3 GPIO_MODER_MODER3
9060#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0
9061#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1
9062#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos
9063#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk
9064#define GPIO_MODER_MODE4 GPIO_MODER_MODER4
9065#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0
9066#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1
9067#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos
9068#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk
9069#define GPIO_MODER_MODE5 GPIO_MODER_MODER5
9070#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0
9071#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1
9072#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos
9073#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk
9074#define GPIO_MODER_MODE6 GPIO_MODER_MODER6
9075#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0
9076#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1
9077#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos
9078#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk
9079#define GPIO_MODER_MODE7 GPIO_MODER_MODER7
9080#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
9081#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
9082#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
9083#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
9084#define GPIO_MODER_MODE8 GPIO_MODER_MODER8
9085#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
9086#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
9087#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos
9088#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk
9089#define GPIO_MODER_MODE9 GPIO_MODER_MODER9
9090#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
9091#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
9092#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
9093#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
9094#define GPIO_MODER_MODE10 GPIO_MODER_MODER10
9095#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
9096#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
9097#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
9098#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
9099#define GPIO_MODER_MODE11 GPIO_MODER_MODER11
9100#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
9101#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
9102#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
9103#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
9104#define GPIO_MODER_MODE12 GPIO_MODER_MODER12
9105#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
9106#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
9107#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
9108#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
9109#define GPIO_MODER_MODE13 GPIO_MODER_MODER13
9110#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
9111#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
9112#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
9113#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
9114#define GPIO_MODER_MODE14 GPIO_MODER_MODER14
9115#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
9116#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
9117#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
9118#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
9119#define GPIO_MODER_MODE15 GPIO_MODER_MODER15
9120#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
9121#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
9122
9123/****************** Bits definition for GPIO_OTYPER register ****************/
9124#define GPIO_OTYPER_OT0_Pos (0U)
9125#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
9126#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
9127#define GPIO_OTYPER_OT1_Pos (1U)
9128#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
9129#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
9130#define GPIO_OTYPER_OT2_Pos (2U)
9131#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
9132#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
9133#define GPIO_OTYPER_OT3_Pos (3U)
9134#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
9135#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
9136#define GPIO_OTYPER_OT4_Pos (4U)
9137#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
9138#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
9139#define GPIO_OTYPER_OT5_Pos (5U)
9140#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
9141#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
9142#define GPIO_OTYPER_OT6_Pos (6U)
9143#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
9144#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
9145#define GPIO_OTYPER_OT7_Pos (7U)
9146#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
9147#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
9148#define GPIO_OTYPER_OT8_Pos (8U)
9149#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
9150#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
9151#define GPIO_OTYPER_OT9_Pos (9U)
9152#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
9153#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
9154#define GPIO_OTYPER_OT10_Pos (10U)
9155#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
9156#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
9157#define GPIO_OTYPER_OT11_Pos (11U)
9158#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
9159#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
9160#define GPIO_OTYPER_OT12_Pos (12U)
9161#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
9162#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
9163#define GPIO_OTYPER_OT13_Pos (13U)
9164#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
9165#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
9166#define GPIO_OTYPER_OT14_Pos (14U)
9167#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
9168#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
9169#define GPIO_OTYPER_OT15_Pos (15U)
9170#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
9171#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
9172
9173/* Legacy defines */
9174#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
9175#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
9176#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
9177#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
9178#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
9179#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
9180#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
9181#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
9182#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
9183#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
9184#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
9185#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
9186#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
9187#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
9188#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
9189#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
9190
9191/****************** Bits definition for GPIO_OSPEEDR register ***************/
9192#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
9193#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
9194#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
9195#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
9196#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
9197#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
9198#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
9199#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
9200#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
9201#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
9202#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
9203#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
9204#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
9205#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
9206#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
9207#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
9208#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
9209#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
9210#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
9211#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
9212#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
9213#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
9214#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
9215#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
9216#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
9217#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
9218#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
9219#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
9220#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
9221#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
9222#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
9223#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
9224#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
9225#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
9226#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
9227#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
9228#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
9229#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
9230#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
9231#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
9232#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
9233#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
9234#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
9235#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
9236#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
9237#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
9238#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
9239#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
9240#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
9241#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
9242#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
9243#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
9244#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
9245#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
9246#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
9247#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
9248#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
9249#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
9250#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
9251#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
9252#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
9253#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
9254#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
9255#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
9256#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
9257#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
9258#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
9259#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
9260#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
9261#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
9262#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
9263#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
9264#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
9265#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
9266#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
9267#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
9268#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
9269#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
9270#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
9271#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
9272
9273/* Legacy defines */
9274#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
9275#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
9276#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
9277#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
9278#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
9279#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
9280#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
9281#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
9282#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
9283#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
9284#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
9285#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
9286#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
9287#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
9288#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
9289#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
9290#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
9291#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
9292#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
9293#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
9294#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
9295#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
9296#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
9297#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
9298#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
9299#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
9300#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
9301#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
9302#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
9303#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
9304#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
9305#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
9306#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
9307#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
9308#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
9309#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
9310#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
9311#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
9312#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
9313#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
9314#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
9315#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
9316#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
9317#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
9318#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
9319#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
9320#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
9321#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
9322
9323/****************** Bits definition for GPIO_PUPDR register *****************/
9324#define GPIO_PUPDR_PUPD0_Pos (0U)
9325#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
9326#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
9327#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
9328#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
9329#define GPIO_PUPDR_PUPD1_Pos (2U)
9330#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
9331#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
9332#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
9333#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
9334#define GPIO_PUPDR_PUPD2_Pos (4U)
9335#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
9336#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
9337#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
9338#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
9339#define GPIO_PUPDR_PUPD3_Pos (6U)
9340#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
9341#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
9342#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
9343#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
9344#define GPIO_PUPDR_PUPD4_Pos (8U)
9345#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
9346#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
9347#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
9348#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
9349#define GPIO_PUPDR_PUPD5_Pos (10U)
9350#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
9351#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
9352#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
9353#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
9354#define GPIO_PUPDR_PUPD6_Pos (12U)
9355#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
9356#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
9357#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
9358#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
9359#define GPIO_PUPDR_PUPD7_Pos (14U)
9360#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
9361#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
9362#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
9363#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
9364#define GPIO_PUPDR_PUPD8_Pos (16U)
9365#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
9366#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
9367#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
9368#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
9369#define GPIO_PUPDR_PUPD9_Pos (18U)
9370#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
9371#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
9372#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
9373#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
9374#define GPIO_PUPDR_PUPD10_Pos (20U)
9375#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
9376#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
9377#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
9378#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
9379#define GPIO_PUPDR_PUPD11_Pos (22U)
9380#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
9381#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
9382#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
9383#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
9384#define GPIO_PUPDR_PUPD12_Pos (24U)
9385#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
9386#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
9387#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
9388#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
9389#define GPIO_PUPDR_PUPD13_Pos (26U)
9390#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
9391#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
9392#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
9393#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
9394#define GPIO_PUPDR_PUPD14_Pos (28U)
9395#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
9396#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
9397#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
9398#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
9399#define GPIO_PUPDR_PUPD15_Pos (30U)
9400#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
9401#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
9402#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
9403#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
9404
9405/* Legacy defines */
9406#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
9407#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
9408#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
9409#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
9410#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
9411#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
9412#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
9413#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
9414#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
9415#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
9416#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
9417#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
9418#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
9419#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
9420#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
9421#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
9422#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
9423#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
9424#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
9425#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
9426#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
9427#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
9428#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
9429#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
9430#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
9431#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
9432#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
9433#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
9434#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
9435#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
9436#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
9437#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
9438#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
9439#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
9440#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
9441#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
9442#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
9443#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
9444#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
9445#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
9446#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
9447#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
9448#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
9449#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
9450#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
9451#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
9452#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
9453#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
9454
9455/****************** Bits definition for GPIO_IDR register *******************/
9456#define GPIO_IDR_ID0_Pos (0U)
9457#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
9458#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
9459#define GPIO_IDR_ID1_Pos (1U)
9460#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
9461#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
9462#define GPIO_IDR_ID2_Pos (2U)
9463#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
9464#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
9465#define GPIO_IDR_ID3_Pos (3U)
9466#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
9467#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
9468#define GPIO_IDR_ID4_Pos (4U)
9469#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
9470#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
9471#define GPIO_IDR_ID5_Pos (5U)
9472#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
9473#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
9474#define GPIO_IDR_ID6_Pos (6U)
9475#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
9476#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
9477#define GPIO_IDR_ID7_Pos (7U)
9478#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
9479#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
9480#define GPIO_IDR_ID8_Pos (8U)
9481#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
9482#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
9483#define GPIO_IDR_ID9_Pos (9U)
9484#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
9485#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
9486#define GPIO_IDR_ID10_Pos (10U)
9487#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
9488#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
9489#define GPIO_IDR_ID11_Pos (11U)
9490#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
9491#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
9492#define GPIO_IDR_ID12_Pos (12U)
9493#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
9494#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
9495#define GPIO_IDR_ID13_Pos (13U)
9496#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
9497#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
9498#define GPIO_IDR_ID14_Pos (14U)
9499#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
9500#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
9501#define GPIO_IDR_ID15_Pos (15U)
9502#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
9503#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
9504
9505/* Legacy defines */
9506#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
9507#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
9508#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
9509#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
9510#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
9511#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
9512#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
9513#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
9514#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
9515#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
9516#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
9517#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
9518#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
9519#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
9520#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
9521#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
9522
9523/****************** Bits definition for GPIO_ODR register *******************/
9524#define GPIO_ODR_OD0_Pos (0U)
9525#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
9526#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
9527#define GPIO_ODR_OD1_Pos (1U)
9528#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
9529#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
9530#define GPIO_ODR_OD2_Pos (2U)
9531#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
9532#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
9533#define GPIO_ODR_OD3_Pos (3U)
9534#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
9535#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
9536#define GPIO_ODR_OD4_Pos (4U)
9537#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
9538#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
9539#define GPIO_ODR_OD5_Pos (5U)
9540#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
9541#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
9542#define GPIO_ODR_OD6_Pos (6U)
9543#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
9544#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
9545#define GPIO_ODR_OD7_Pos (7U)
9546#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
9547#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
9548#define GPIO_ODR_OD8_Pos (8U)
9549#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
9550#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
9551#define GPIO_ODR_OD9_Pos (9U)
9552#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
9553#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
9554#define GPIO_ODR_OD10_Pos (10U)
9555#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
9556#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
9557#define GPIO_ODR_OD11_Pos (11U)
9558#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
9559#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
9560#define GPIO_ODR_OD12_Pos (12U)
9561#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
9562#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
9563#define GPIO_ODR_OD13_Pos (13U)
9564#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
9565#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
9566#define GPIO_ODR_OD14_Pos (14U)
9567#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
9568#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
9569#define GPIO_ODR_OD15_Pos (15U)
9570#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
9571#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
9572/* Legacy defines */
9573#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
9574#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
9575#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
9576#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
9577#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
9578#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
9579#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
9580#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
9581#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
9582#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
9583#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
9584#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
9585#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
9586#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
9587#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
9588#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
9589
9590/****************** Bits definition for GPIO_BSRR register ******************/
9591#define GPIO_BSRR_BS0_Pos (0U)
9592#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
9593#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
9594#define GPIO_BSRR_BS1_Pos (1U)
9595#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
9596#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
9597#define GPIO_BSRR_BS2_Pos (2U)
9598#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
9599#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
9600#define GPIO_BSRR_BS3_Pos (3U)
9601#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
9602#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
9603#define GPIO_BSRR_BS4_Pos (4U)
9604#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
9605#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
9606#define GPIO_BSRR_BS5_Pos (5U)
9607#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
9608#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
9609#define GPIO_BSRR_BS6_Pos (6U)
9610#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
9611#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
9612#define GPIO_BSRR_BS7_Pos (7U)
9613#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
9614#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
9615#define GPIO_BSRR_BS8_Pos (8U)
9616#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
9617#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
9618#define GPIO_BSRR_BS9_Pos (9U)
9619#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
9620#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
9621#define GPIO_BSRR_BS10_Pos (10U)
9622#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
9623#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
9624#define GPIO_BSRR_BS11_Pos (11U)
9625#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
9626#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
9627#define GPIO_BSRR_BS12_Pos (12U)
9628#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
9629#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
9630#define GPIO_BSRR_BS13_Pos (13U)
9631#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
9632#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
9633#define GPIO_BSRR_BS14_Pos (14U)
9634#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
9635#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
9636#define GPIO_BSRR_BS15_Pos (15U)
9637#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
9638#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
9639#define GPIO_BSRR_BR0_Pos (16U)
9640#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
9641#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
9642#define GPIO_BSRR_BR1_Pos (17U)
9643#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
9644#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
9645#define GPIO_BSRR_BR2_Pos (18U)
9646#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
9647#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
9648#define GPIO_BSRR_BR3_Pos (19U)
9649#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
9650#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
9651#define GPIO_BSRR_BR4_Pos (20U)
9652#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
9653#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
9654#define GPIO_BSRR_BR5_Pos (21U)
9655#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
9656#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
9657#define GPIO_BSRR_BR6_Pos (22U)
9658#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
9659#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
9660#define GPIO_BSRR_BR7_Pos (23U)
9661#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
9662#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
9663#define GPIO_BSRR_BR8_Pos (24U)
9664#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
9665#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
9666#define GPIO_BSRR_BR9_Pos (25U)
9667#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
9668#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
9669#define GPIO_BSRR_BR10_Pos (26U)
9670#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
9671#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
9672#define GPIO_BSRR_BR11_Pos (27U)
9673#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
9674#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
9675#define GPIO_BSRR_BR12_Pos (28U)
9676#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
9677#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
9678#define GPIO_BSRR_BR13_Pos (29U)
9679#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
9680#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
9681#define GPIO_BSRR_BR14_Pos (30U)
9682#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
9683#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
9684#define GPIO_BSRR_BR15_Pos (31U)
9685#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
9686#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
9687
9688/* Legacy defines */
9689#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
9690#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
9691#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
9692#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
9693#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
9694#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
9695#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
9696#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
9697#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
9698#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
9699#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
9700#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
9701#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
9702#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
9703#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
9704#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
9705#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
9706#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
9707#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
9708#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
9709#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
9710#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
9711#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
9712#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
9713#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
9714#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
9715#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
9716#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
9717#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
9718#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
9719#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
9720#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
9721#define GPIO_BRR_BR0 GPIO_BSRR_BR0
9722#define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
9723#define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
9724#define GPIO_BRR_BR1 GPIO_BSRR_BR1
9725#define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
9726#define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
9727#define GPIO_BRR_BR2 GPIO_BSRR_BR2
9728#define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
9729#define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
9730#define GPIO_BRR_BR3 GPIO_BSRR_BR3
9731#define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
9732#define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
9733#define GPIO_BRR_BR4 GPIO_BSRR_BR4
9734#define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
9735#define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
9736#define GPIO_BRR_BR5 GPIO_BSRR_BR5
9737#define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
9738#define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
9739#define GPIO_BRR_BR6 GPIO_BSRR_BR6
9740#define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
9741#define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
9742#define GPIO_BRR_BR7 GPIO_BSRR_BR7
9743#define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
9744#define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
9745#define GPIO_BRR_BR8 GPIO_BSRR_BR8
9746#define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
9747#define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
9748#define GPIO_BRR_BR9 GPIO_BSRR_BR9
9749#define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
9750#define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
9751#define GPIO_BRR_BR10 GPIO_BSRR_BR10
9752#define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
9753#define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
9754#define GPIO_BRR_BR11 GPIO_BSRR_BR11
9755#define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
9756#define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
9757#define GPIO_BRR_BR12 GPIO_BSRR_BR12
9758#define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
9759#define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
9760#define GPIO_BRR_BR13 GPIO_BSRR_BR13
9761#define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
9762#define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
9763#define GPIO_BRR_BR14 GPIO_BSRR_BR14
9764#define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
9765#define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
9766#define GPIO_BRR_BR15 GPIO_BSRR_BR15
9767#define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
9768#define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
9769/****************** Bit definition for GPIO_LCKR register *********************/
9770#define GPIO_LCKR_LCK0_Pos (0U)
9771#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
9772#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
9773#define GPIO_LCKR_LCK1_Pos (1U)
9774#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
9775#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
9776#define GPIO_LCKR_LCK2_Pos (2U)
9777#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
9778#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
9779#define GPIO_LCKR_LCK3_Pos (3U)
9780#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
9781#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
9782#define GPIO_LCKR_LCK4_Pos (4U)
9783#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
9784#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
9785#define GPIO_LCKR_LCK5_Pos (5U)
9786#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
9787#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
9788#define GPIO_LCKR_LCK6_Pos (6U)
9789#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
9790#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
9791#define GPIO_LCKR_LCK7_Pos (7U)
9792#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
9793#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
9794#define GPIO_LCKR_LCK8_Pos (8U)
9795#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
9796#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
9797#define GPIO_LCKR_LCK9_Pos (9U)
9798#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
9799#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
9800#define GPIO_LCKR_LCK10_Pos (10U)
9801#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
9802#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
9803#define GPIO_LCKR_LCK11_Pos (11U)
9804#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
9805#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
9806#define GPIO_LCKR_LCK12_Pos (12U)
9807#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
9808#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
9809#define GPIO_LCKR_LCK13_Pos (13U)
9810#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
9811#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
9812#define GPIO_LCKR_LCK14_Pos (14U)
9813#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
9814#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
9815#define GPIO_LCKR_LCK15_Pos (15U)
9816#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
9817#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
9818#define GPIO_LCKR_LCKK_Pos (16U)
9819#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
9820#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
9821/****************** Bit definition for GPIO_AFRL register *********************/
9822#define GPIO_AFRL_AFSEL0_Pos (0U)
9823#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
9824#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
9825#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
9826#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
9827#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
9828#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
9829#define GPIO_AFRL_AFSEL1_Pos (4U)
9830#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
9831#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
9832#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
9833#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
9834#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
9835#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
9836#define GPIO_AFRL_AFSEL2_Pos (8U)
9837#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
9838#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
9839#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
9840#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
9841#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
9842#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
9843#define GPIO_AFRL_AFSEL3_Pos (12U)
9844#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
9845#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
9846#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
9847#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
9848#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
9849#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
9850#define GPIO_AFRL_AFSEL4_Pos (16U)
9851#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
9852#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
9853#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
9854#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
9855#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
9856#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
9857#define GPIO_AFRL_AFSEL5_Pos (20U)
9858#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
9859#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
9860#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
9861#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
9862#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
9863#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
9864#define GPIO_AFRL_AFSEL6_Pos (24U)
9865#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
9866#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
9867#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
9868#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
9869#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
9870#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
9871#define GPIO_AFRL_AFSEL7_Pos (28U)
9872#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
9873#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
9874#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
9875#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
9876#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
9877#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
9878
9879/* Legacy defines */
9880#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
9881#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
9882#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
9883#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
9884#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
9885#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
9886#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
9887#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
9888#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
9889#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
9890#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
9891#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
9892#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
9893#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
9894#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
9895#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
9896#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
9897#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
9898#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
9899#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
9900#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
9901#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
9902#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
9903#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
9904#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
9905#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
9906#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
9907#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
9908#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
9909#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
9910#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
9911#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
9912#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
9913#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
9914#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
9915#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
9916#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
9917#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
9918#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
9919#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
9920
9921/****************** Bit definition for GPIO_AFRH register *********************/
9922#define GPIO_AFRH_AFSEL8_Pos (0U)
9923#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
9924#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
9925#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
9926#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
9927#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
9928#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
9929#define GPIO_AFRH_AFSEL9_Pos (4U)
9930#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
9931#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
9932#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
9933#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
9934#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
9935#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
9936#define GPIO_AFRH_AFSEL10_Pos (8U)
9937#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
9938#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
9939#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
9940#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
9941#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
9942#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
9943#define GPIO_AFRH_AFSEL11_Pos (12U)
9944#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
9945#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
9946#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
9947#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
9948#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
9949#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
9950#define GPIO_AFRH_AFSEL12_Pos (16U)
9951#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
9952#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
9953#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
9954#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
9955#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
9956#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
9957#define GPIO_AFRH_AFSEL13_Pos (20U)
9958#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
9959#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
9960#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
9961#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
9962#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
9963#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
9964#define GPIO_AFRH_AFSEL14_Pos (24U)
9965#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
9966#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
9967#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
9968#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
9969#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
9970#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
9971#define GPIO_AFRH_AFSEL15_Pos (28U)
9972#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
9973#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
9974#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
9975#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
9976#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
9977#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
9978
9979/* Legacy defines */
9980#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
9981#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
9982#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
9983#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
9984#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
9985#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
9986#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
9987#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
9988#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
9989#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
9990#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
9991#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
9992#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
9993#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
9994#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
9995#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
9996#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
9997#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
9998#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
9999#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
10000#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
10001#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
10002#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
10003#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
10004#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
10005#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
10006#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
10007#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
10008#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
10009#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
10010#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
10011#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
10012#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
10013#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
10014#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
10015#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
10016#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
10017#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
10018#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
10019#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
10020
10021
10022/******************************************************************************/
10023/* */
10024/* HASH */
10025/* */
10026/******************************************************************************/
10027/****************** Bits definition for HASH_CR register ********************/
10028#define HASH_CR_INIT_Pos (2U)
10029#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos)
10030#define HASH_CR_INIT HASH_CR_INIT_Msk
10031#define HASH_CR_DMAE_Pos (3U)
10032#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos)
10033#define HASH_CR_DMAE HASH_CR_DMAE_Msk
10034#define HASH_CR_DATATYPE_Pos (4U)
10035#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos)
10036#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
10037#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos)
10038#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos)
10039#define HASH_CR_MODE_Pos (6U)
10040#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos)
10041#define HASH_CR_MODE HASH_CR_MODE_Msk
10042#define HASH_CR_ALGO_Pos (7U)
10043#define HASH_CR_ALGO_Msk (0x801UL << HASH_CR_ALGO_Pos)
10044#define HASH_CR_ALGO HASH_CR_ALGO_Msk
10045#define HASH_CR_ALGO_0 (0x001UL << HASH_CR_ALGO_Pos)
10046#define HASH_CR_ALGO_1 (0x800UL << HASH_CR_ALGO_Pos)
10047#define HASH_CR_NBW_Pos (8U)
10048#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos)
10049#define HASH_CR_NBW HASH_CR_NBW_Msk
10050#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos)
10051#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos)
10052#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos)
10053#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos)
10054#define HASH_CR_DINNE_Pos (12U)
10055#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos)
10056#define HASH_CR_DINNE HASH_CR_DINNE_Msk
10057#define HASH_CR_MDMAT_Pos (13U)
10058#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos)
10059#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
10060#define HASH_CR_LKEY_Pos (16U)
10061#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos)
10062#define HASH_CR_LKEY HASH_CR_LKEY_Msk
10063
10064/****************** Bits definition for HASH_STR register *******************/
10065#define HASH_STR_NBLW_Pos (0U)
10066#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos)
10067#define HASH_STR_NBLW HASH_STR_NBLW_Msk
10068#define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos)
10069#define HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos)
10070#define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos)
10071#define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos)
10072#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos)
10073#define HASH_STR_DCAL_Pos (8U)
10074#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos)
10075#define HASH_STR_DCAL HASH_STR_DCAL_Msk
10076/* Aliases for HASH_STR register */
10077#define HASH_STR_NBW HASH_STR_NBLW
10078#define HASH_STR_NBW_0 HASH_STR_NBLW_0
10079#define HASH_STR_NBW_1 HASH_STR_NBLW_1
10080#define HASH_STR_NBW_2 HASH_STR_NBLW_2
10081#define HASH_STR_NBW_3 HASH_STR_NBLW_3
10082#define HASH_STR_NBW_4 HASH_STR_NBLW_4
10083
10084/****************** Bits definition for HASH_IMR register *******************/
10085#define HASH_IMR_DINIE_Pos (0U)
10086#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos)
10087#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
10088#define HASH_IMR_DCIE_Pos (1U)
10089#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos)
10090#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
10091/* Aliases for HASH_IMR register */
10092#define HASH_IMR_DINIM HASH_IMR_DINIE
10093#define HASH_IMR_DCIM HASH_IMR_DCIE
10094
10095/****************** Bits definition for HASH_SR register ********************/
10096#define HASH_SR_DINIS_Pos (0U)
10097#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos)
10098#define HASH_SR_DINIS HASH_SR_DINIS_Msk
10099#define HASH_SR_DCIS_Pos (1U)
10100#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos)
10101#define HASH_SR_DCIS HASH_SR_DCIS_Msk
10102#define HASH_SR_DMAS_Pos (2U)
10103#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos)
10104#define HASH_SR_DMAS HASH_SR_DMAS_Msk
10105#define HASH_SR_BUSY_Pos (3U)
10106#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos)
10107#define HASH_SR_BUSY HASH_SR_BUSY_Msk
10108
10109/******************************************************************************/
10110/* */
10111/* Inter-integrated Circuit Interface */
10112/* */
10113/******************************************************************************/
10114/******************* Bit definition for I2C_CR1 register ********************/
10115#define I2C_CR1_PE_Pos (0U)
10116#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
10117#define I2C_CR1_PE I2C_CR1_PE_Msk
10118#define I2C_CR1_SMBUS_Pos (1U)
10119#define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)
10120#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk
10121#define I2C_CR1_SMBTYPE_Pos (3U)
10122#define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)
10123#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk
10124#define I2C_CR1_ENARP_Pos (4U)
10125#define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)
10126#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk
10127#define I2C_CR1_ENPEC_Pos (5U)
10128#define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)
10129#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk
10130#define I2C_CR1_ENGC_Pos (6U)
10131#define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)
10132#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk
10133#define I2C_CR1_NOSTRETCH_Pos (7U)
10134#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
10135#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
10136#define I2C_CR1_START_Pos (8U)
10137#define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)
10138#define I2C_CR1_START I2C_CR1_START_Msk
10139#define I2C_CR1_STOP_Pos (9U)
10140#define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)
10141#define I2C_CR1_STOP I2C_CR1_STOP_Msk
10142#define I2C_CR1_ACK_Pos (10U)
10143#define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)
10144#define I2C_CR1_ACK I2C_CR1_ACK_Msk
10145#define I2C_CR1_POS_Pos (11U)
10146#define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)
10147#define I2C_CR1_POS I2C_CR1_POS_Msk
10148#define I2C_CR1_PEC_Pos (12U)
10149#define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)
10150#define I2C_CR1_PEC I2C_CR1_PEC_Msk
10151#define I2C_CR1_ALERT_Pos (13U)
10152#define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)
10153#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk
10154#define I2C_CR1_SWRST_Pos (15U)
10155#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
10156#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
10157
10158/******************* Bit definition for I2C_CR2 register ********************/
10159#define I2C_CR2_FREQ_Pos (0U)
10160#define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)
10161#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk
10162#define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)
10163#define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)
10164#define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)
10165#define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)
10166#define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)
10167#define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)
10168
10169#define I2C_CR2_ITERREN_Pos (8U)
10170#define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)
10171#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk
10172#define I2C_CR2_ITEVTEN_Pos (9U)
10173#define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)
10174#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk
10175#define I2C_CR2_ITBUFEN_Pos (10U)
10176#define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)
10177#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk
10178#define I2C_CR2_DMAEN_Pos (11U)
10179#define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)
10180#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk
10181#define I2C_CR2_LAST_Pos (12U)
10182#define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)
10183#define I2C_CR2_LAST I2C_CR2_LAST_Msk
10184
10185/******************* Bit definition for I2C_OAR1 register *******************/
10186#define I2C_OAR1_ADD1_7 0x000000FEU
10187#define I2C_OAR1_ADD8_9 0x00000300U
10188
10189#define I2C_OAR1_ADD0_Pos (0U)
10190#define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)
10191#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk
10192#define I2C_OAR1_ADD1_Pos (1U)
10193#define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)
10194#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk
10195#define I2C_OAR1_ADD2_Pos (2U)
10196#define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)
10197#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk
10198#define I2C_OAR1_ADD3_Pos (3U)
10199#define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)
10200#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk
10201#define I2C_OAR1_ADD4_Pos (4U)
10202#define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)
10203#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk
10204#define I2C_OAR1_ADD5_Pos (5U)
10205#define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)
10206#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk
10207#define I2C_OAR1_ADD6_Pos (6U)
10208#define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)
10209#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk
10210#define I2C_OAR1_ADD7_Pos (7U)
10211#define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)
10212#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk
10213#define I2C_OAR1_ADD8_Pos (8U)
10214#define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)
10215#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk
10216#define I2C_OAR1_ADD9_Pos (9U)
10217#define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)
10218#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk
10219
10220#define I2C_OAR1_ADDMODE_Pos (15U)
10221#define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)
10222#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk
10223
10224/******************* Bit definition for I2C_OAR2 register *******************/
10225#define I2C_OAR2_ENDUAL_Pos (0U)
10226#define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)
10227#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk
10228#define I2C_OAR2_ADD2_Pos (1U)
10229#define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)
10230#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk
10231
10232/******************** Bit definition for I2C_DR register ********************/
10233#define I2C_DR_DR_Pos (0U)
10234#define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)
10235#define I2C_DR_DR I2C_DR_DR_Msk
10236
10237/******************* Bit definition for I2C_SR1 register ********************/
10238#define I2C_SR1_SB_Pos (0U)
10239#define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)
10240#define I2C_SR1_SB I2C_SR1_SB_Msk
10241#define I2C_SR1_ADDR_Pos (1U)
10242#define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)
10243#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk
10244#define I2C_SR1_BTF_Pos (2U)
10245#define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)
10246#define I2C_SR1_BTF I2C_SR1_BTF_Msk
10247#define I2C_SR1_ADD10_Pos (3U)
10248#define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)
10249#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk
10250#define I2C_SR1_STOPF_Pos (4U)
10251#define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)
10252#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk
10253#define I2C_SR1_RXNE_Pos (6U)
10254#define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)
10255#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk
10256#define I2C_SR1_TXE_Pos (7U)
10257#define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)
10258#define I2C_SR1_TXE I2C_SR1_TXE_Msk
10259#define I2C_SR1_BERR_Pos (8U)
10260#define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)
10261#define I2C_SR1_BERR I2C_SR1_BERR_Msk
10262#define I2C_SR1_ARLO_Pos (9U)
10263#define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)
10264#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk
10265#define I2C_SR1_AF_Pos (10U)
10266#define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)
10267#define I2C_SR1_AF I2C_SR1_AF_Msk
10268#define I2C_SR1_OVR_Pos (11U)
10269#define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)
10270#define I2C_SR1_OVR I2C_SR1_OVR_Msk
10271#define I2C_SR1_PECERR_Pos (12U)
10272#define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)
10273#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk
10274#define I2C_SR1_TIMEOUT_Pos (14U)
10275#define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)
10276#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk
10277#define I2C_SR1_SMBALERT_Pos (15U)
10278#define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)
10279#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk
10280
10281/******************* Bit definition for I2C_SR2 register ********************/
10282#define I2C_SR2_MSL_Pos (0U)
10283#define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)
10284#define I2C_SR2_MSL I2C_SR2_MSL_Msk
10285#define I2C_SR2_BUSY_Pos (1U)
10286#define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)
10287#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk
10288#define I2C_SR2_TRA_Pos (2U)
10289#define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)
10290#define I2C_SR2_TRA I2C_SR2_TRA_Msk
10291#define I2C_SR2_GENCALL_Pos (4U)
10292#define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)
10293#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk
10294#define I2C_SR2_SMBDEFAULT_Pos (5U)
10295#define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
10296#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk
10297#define I2C_SR2_SMBHOST_Pos (6U)
10298#define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)
10299#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk
10300#define I2C_SR2_DUALF_Pos (7U)
10301#define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)
10302#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk
10303#define I2C_SR2_PEC_Pos (8U)
10304#define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)
10305#define I2C_SR2_PEC I2C_SR2_PEC_Msk
10306
10307/******************* Bit definition for I2C_CCR register ********************/
10308#define I2C_CCR_CCR_Pos (0U)
10309#define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)
10310#define I2C_CCR_CCR I2C_CCR_CCR_Msk
10311#define I2C_CCR_DUTY_Pos (14U)
10312#define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)
10313#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk
10314#define I2C_CCR_FS_Pos (15U)
10315#define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)
10316#define I2C_CCR_FS I2C_CCR_FS_Msk
10317
10318/****************** Bit definition for I2C_TRISE register *******************/
10319#define I2C_TRISE_TRISE_Pos (0U)
10320#define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)
10321#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk
10322
10323/****************** Bit definition for I2C_FLTR register *******************/
10324#define I2C_FLTR_DNF_Pos (0U)
10325#define I2C_FLTR_DNF_Msk (0xFUL << I2C_FLTR_DNF_Pos)
10326#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk
10327#define I2C_FLTR_ANOFF_Pos (4U)
10328#define I2C_FLTR_ANOFF_Msk (0x1UL << I2C_FLTR_ANOFF_Pos)
10329#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk
10330
10331/******************************************************************************/
10332/* */
10333/* Independent WATCHDOG */
10334/* */
10335/******************************************************************************/
10336/******************* Bit definition for IWDG_KR register ********************/
10337#define IWDG_KR_KEY_Pos (0U)
10338#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
10339#define IWDG_KR_KEY IWDG_KR_KEY_Msk
10340
10341/******************* Bit definition for IWDG_PR register ********************/
10342#define IWDG_PR_PR_Pos (0U)
10343#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
10344#define IWDG_PR_PR IWDG_PR_PR_Msk
10345#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
10346#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
10347#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
10348
10349/******************* Bit definition for IWDG_RLR register *******************/
10350#define IWDG_RLR_RL_Pos (0U)
10351#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
10352#define IWDG_RLR_RL IWDG_RLR_RL_Msk
10353
10354/******************* Bit definition for IWDG_SR register ********************/
10355#define IWDG_SR_PVU_Pos (0U)
10356#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
10357#define IWDG_SR_PVU IWDG_SR_PVU_Msk
10358#define IWDG_SR_RVU_Pos (1U)
10359#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
10360#define IWDG_SR_RVU IWDG_SR_RVU_Msk
10361
10362
10363/******************************************************************************/
10364/* */
10365/* LCD-TFT Display Controller (LTDC) */
10366/* */
10367/******************************************************************************/
10368
10369/******************** Bit definition for LTDC_SSCR register *****************/
10370
10371#define LTDC_SSCR_VSH_Pos (0U)
10372#define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos)
10373#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk
10374#define LTDC_SSCR_HSW_Pos (16U)
10375#define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos)
10376#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk
10377
10378/******************** Bit definition for LTDC_BPCR register *****************/
10379
10380#define LTDC_BPCR_AVBP_Pos (0U)
10381#define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos)
10382#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk
10383#define LTDC_BPCR_AHBP_Pos (16U)
10384#define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos)
10385#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk
10386
10387/******************** Bit definition for LTDC_AWCR register *****************/
10388
10389#define LTDC_AWCR_AAH_Pos (0U)
10390#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos)
10391#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk
10392#define LTDC_AWCR_AAW_Pos (16U)
10393#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos)
10394#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk
10395
10396/******************** Bit definition for LTDC_TWCR register *****************/
10397
10398#define LTDC_TWCR_TOTALH_Pos (0U)
10399#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos)
10400#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk
10401#define LTDC_TWCR_TOTALW_Pos (16U)
10402#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos)
10403#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk
10404
10405/******************** Bit definition for LTDC_GCR register ******************/
10406
10407#define LTDC_GCR_LTDCEN_Pos (0U)
10408#define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos)
10409#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk
10410#define LTDC_GCR_DBW_Pos (4U)
10411#define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos)
10412#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk
10413#define LTDC_GCR_DGW_Pos (8U)
10414#define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos)
10415#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk
10416#define LTDC_GCR_DRW_Pos (12U)
10417#define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos)
10418#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk
10419#define LTDC_GCR_DEN_Pos (16U)
10420#define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos)
10421#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk
10422#define LTDC_GCR_PCPOL_Pos (28U)
10423#define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos)
10424#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk
10425#define LTDC_GCR_DEPOL_Pos (29U)
10426#define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos)
10427#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk
10428#define LTDC_GCR_VSPOL_Pos (30U)
10429#define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos)
10430#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk
10431#define LTDC_GCR_HSPOL_Pos (31U)
10432#define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos)
10433#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk
10434
10435/* Legacy defines */
10436#define LTDC_GCR_DTEN LTDC_GCR_DEN
10437
10438/******************** Bit definition for LTDC_SRCR register *****************/
10439
10440#define LTDC_SRCR_IMR_Pos (0U)
10441#define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos)
10442#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk
10443#define LTDC_SRCR_VBR_Pos (1U)
10444#define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos)
10445#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk
10446
10447/******************** Bit definition for LTDC_BCCR register *****************/
10448
10449#define LTDC_BCCR_BCBLUE_Pos (0U)
10450#define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos)
10451#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk
10452#define LTDC_BCCR_BCGREEN_Pos (8U)
10453#define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos)
10454#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk
10455#define LTDC_BCCR_BCRED_Pos (16U)
10456#define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos)
10457#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk
10458
10459/******************** Bit definition for LTDC_IER register ******************/
10460
10461#define LTDC_IER_LIE_Pos (0U)
10462#define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos)
10463#define LTDC_IER_LIE LTDC_IER_LIE_Msk
10464#define LTDC_IER_FUIE_Pos (1U)
10465#define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos)
10466#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk
10467#define LTDC_IER_TERRIE_Pos (2U)
10468#define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos)
10469#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk
10470#define LTDC_IER_RRIE_Pos (3U)
10471#define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos)
10472#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk
10473
10474/******************** Bit definition for LTDC_ISR register ******************/
10475
10476#define LTDC_ISR_LIF_Pos (0U)
10477#define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos)
10478#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk
10479#define LTDC_ISR_FUIF_Pos (1U)
10480#define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos)
10481#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk
10482#define LTDC_ISR_TERRIF_Pos (2U)
10483#define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos)
10484#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk
10485#define LTDC_ISR_RRIF_Pos (3U)
10486#define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos)
10487#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk
10488
10489/******************** Bit definition for LTDC_ICR register ******************/
10490
10491#define LTDC_ICR_CLIF_Pos (0U)
10492#define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos)
10493#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk
10494#define LTDC_ICR_CFUIF_Pos (1U)
10495#define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos)
10496#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk
10497#define LTDC_ICR_CTERRIF_Pos (2U)
10498#define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos)
10499#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk
10500#define LTDC_ICR_CRRIF_Pos (3U)
10501#define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos)
10502#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk
10503
10504/******************** Bit definition for LTDC_LIPCR register ****************/
10505
10506#define LTDC_LIPCR_LIPOS_Pos (0U)
10507#define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)
10508#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk
10509
10510/******************** Bit definition for LTDC_CPSR register *****************/
10511
10512#define LTDC_CPSR_CYPOS_Pos (0U)
10513#define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)
10514#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk
10515#define LTDC_CPSR_CXPOS_Pos (16U)
10516#define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)
10517#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk
10518
10519/******************** Bit definition for LTDC_CDSR register *****************/
10520
10521#define LTDC_CDSR_VDES_Pos (0U)
10522#define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos)
10523#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk
10524#define LTDC_CDSR_HDES_Pos (1U)
10525#define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos)
10526#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk
10527#define LTDC_CDSR_VSYNCS_Pos (2U)
10528#define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos)
10529#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk
10530#define LTDC_CDSR_HSYNCS_Pos (3U)
10531#define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos)
10532#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk
10533
10534/******************** Bit definition for LTDC_LxCR register *****************/
10535
10536#define LTDC_LxCR_LEN_Pos (0U)
10537#define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos)
10538#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk
10539#define LTDC_LxCR_COLKEN_Pos (1U)
10540#define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos)
10541#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk
10542#define LTDC_LxCR_CLUTEN_Pos (4U)
10543#define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos)
10544#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk
10545
10546/******************** Bit definition for LTDC_LxWHPCR register **************/
10547
10548#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
10549#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)
10550#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk
10551#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
10552#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)
10553#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk
10554
10555/******************** Bit definition for LTDC_LxWVPCR register **************/
10556
10557#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
10558#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)
10559#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk
10560#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
10561#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)
10562#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk
10563
10564/******************** Bit definition for LTDC_LxCKCR register ***************/
10565
10566#define LTDC_LxCKCR_CKBLUE_Pos (0U)
10567#define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)
10568#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk
10569#define LTDC_LxCKCR_CKGREEN_Pos (8U)
10570#define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)
10571#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk
10572#define LTDC_LxCKCR_CKRED_Pos (16U)
10573#define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos)
10574#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk
10575
10576/******************** Bit definition for LTDC_LxPFCR register ***************/
10577
10578#define LTDC_LxPFCR_PF_Pos (0U)
10579#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos)
10580#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk
10581
10582/******************** Bit definition for LTDC_LxCACR register ***************/
10583
10584#define LTDC_LxCACR_CONSTA_Pos (0U)
10585#define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos)
10586#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk
10587
10588/******************** Bit definition for LTDC_LxDCCR register ***************/
10589
10590#define LTDC_LxDCCR_DCBLUE_Pos (0U)
10591#define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)
10592#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk
10593#define LTDC_LxDCCR_DCGREEN_Pos (8U)
10594#define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)
10595#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk
10596#define LTDC_LxDCCR_DCRED_Pos (16U)
10597#define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos)
10598#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk
10599#define LTDC_LxDCCR_DCALPHA_Pos (24U)
10600#define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)
10601#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk
10602
10603/******************** Bit definition for LTDC_LxBFCR register ***************/
10604
10605#define LTDC_LxBFCR_BF2_Pos (0U)
10606#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos)
10607#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk
10608#define LTDC_LxBFCR_BF1_Pos (8U)
10609#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos)
10610#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk
10611
10612/******************** Bit definition for LTDC_LxCFBAR register **************/
10613
10614#define LTDC_LxCFBAR_CFBADD_Pos (0U)
10615#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos)
10616#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk
10617
10618/******************** Bit definition for LTDC_LxCFBLR register **************/
10619
10620#define LTDC_LxCFBLR_CFBLL_Pos (0U)
10621#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)
10622#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk
10623#define LTDC_LxCFBLR_CFBP_Pos (16U)
10624#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)
10625#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk
10626
10627/******************** Bit definition for LTDC_LxCFBLNR register *************/
10628
10629#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
10630#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)
10631#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk
10632
10633/******************** Bit definition for LTDC_LxCLUTWR register *************/
10634
10635#define LTDC_LxCLUTWR_BLUE_Pos (0U)
10636#define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)
10637#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk
10638#define LTDC_LxCLUTWR_GREEN_Pos (8U)
10639#define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)
10640#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk
10641#define LTDC_LxCLUTWR_RED_Pos (16U)
10642#define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos)
10643#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk
10644#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
10645#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)
10646#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk
10647
10648
10649/******************************************************************************/
10650/* */
10651/* Power Control */
10652/* */
10653/******************************************************************************/
10654/******************** Bit definition for PWR_CR register ********************/
10655#define PWR_CR_LPDS_Pos (0U)
10656#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
10657#define PWR_CR_LPDS PWR_CR_LPDS_Msk
10658#define PWR_CR_PDDS_Pos (1U)
10659#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
10660#define PWR_CR_PDDS PWR_CR_PDDS_Msk
10661#define PWR_CR_CWUF_Pos (2U)
10662#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
10663#define PWR_CR_CWUF PWR_CR_CWUF_Msk
10664#define PWR_CR_CSBF_Pos (3U)
10665#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
10666#define PWR_CR_CSBF PWR_CR_CSBF_Msk
10667#define PWR_CR_PVDE_Pos (4U)
10668#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
10669#define PWR_CR_PVDE PWR_CR_PVDE_Msk
10670
10671#define PWR_CR_PLS_Pos (5U)
10672#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
10673#define PWR_CR_PLS PWR_CR_PLS_Msk
10674#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
10675#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
10676#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
10677
10679#define PWR_CR_PLS_LEV0 0x00000000U
10680#define PWR_CR_PLS_LEV1 0x00000020U
10681#define PWR_CR_PLS_LEV2 0x00000040U
10682#define PWR_CR_PLS_LEV3 0x00000060U
10683#define PWR_CR_PLS_LEV4 0x00000080U
10684#define PWR_CR_PLS_LEV5 0x000000A0U
10685#define PWR_CR_PLS_LEV6 0x000000C0U
10686#define PWR_CR_PLS_LEV7 0x000000E0U
10687#define PWR_CR_DBP_Pos (8U)
10688#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
10689#define PWR_CR_DBP PWR_CR_DBP_Msk
10690#define PWR_CR_FPDS_Pos (9U)
10691#define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos)
10692#define PWR_CR_FPDS PWR_CR_FPDS_Msk
10693#define PWR_CR_LPLVDS_Pos (10U)
10694#define PWR_CR_LPLVDS_Msk (0x1UL << PWR_CR_LPLVDS_Pos)
10695#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk
10696#define PWR_CR_MRLVDS_Pos (11U)
10697#define PWR_CR_MRLVDS_Msk (0x1UL << PWR_CR_MRLVDS_Pos)
10698#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk
10699#define PWR_CR_ADCDC1_Pos (13U)
10700#define PWR_CR_ADCDC1_Msk (0x1UL << PWR_CR_ADCDC1_Pos)
10701#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk
10702#define PWR_CR_VOS_Pos (14U)
10703#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos)
10704#define PWR_CR_VOS PWR_CR_VOS_Msk
10705#define PWR_CR_VOS_0 0x00004000U
10706#define PWR_CR_VOS_1 0x00008000U
10707#define PWR_CR_ODEN_Pos (16U)
10708#define PWR_CR_ODEN_Msk (0x1UL << PWR_CR_ODEN_Pos)
10709#define PWR_CR_ODEN PWR_CR_ODEN_Msk
10710#define PWR_CR_ODSWEN_Pos (17U)
10711#define PWR_CR_ODSWEN_Msk (0x1UL << PWR_CR_ODSWEN_Pos)
10712#define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk
10713#define PWR_CR_UDEN_Pos (18U)
10714#define PWR_CR_UDEN_Msk (0x3UL << PWR_CR_UDEN_Pos)
10715#define PWR_CR_UDEN PWR_CR_UDEN_Msk
10716#define PWR_CR_UDEN_0 (0x1UL << PWR_CR_UDEN_Pos)
10717#define PWR_CR_UDEN_1 (0x2UL << PWR_CR_UDEN_Pos)
10718
10719/* Legacy define */
10720#define PWR_CR_PMODE PWR_CR_VOS
10721#define PWR_CR_LPUDS PWR_CR_LPLVDS
10722#define PWR_CR_MRUDS PWR_CR_MRLVDS
10723
10724/******************* Bit definition for PWR_CSR register ********************/
10725#define PWR_CSR_WUF_Pos (0U)
10726#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
10727#define PWR_CSR_WUF PWR_CSR_WUF_Msk
10728#define PWR_CSR_SBF_Pos (1U)
10729#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
10730#define PWR_CSR_SBF PWR_CSR_SBF_Msk
10731#define PWR_CSR_PVDO_Pos (2U)
10732#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
10733#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk
10734#define PWR_CSR_BRR_Pos (3U)
10735#define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos)
10736#define PWR_CSR_BRR PWR_CSR_BRR_Msk
10737#define PWR_CSR_EWUP_Pos (8U)
10738#define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos)
10739#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk
10740#define PWR_CSR_BRE_Pos (9U)
10741#define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos)
10742#define PWR_CSR_BRE PWR_CSR_BRE_Msk
10743#define PWR_CSR_VOSRDY_Pos (14U)
10744#define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos)
10745#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk
10746#define PWR_CSR_ODRDY_Pos (16U)
10747#define PWR_CSR_ODRDY_Msk (0x1UL << PWR_CSR_ODRDY_Pos)
10748#define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk
10749#define PWR_CSR_ODSWRDY_Pos (17U)
10750#define PWR_CSR_ODSWRDY_Msk (0x1UL << PWR_CSR_ODSWRDY_Pos)
10751#define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk
10752#define PWR_CSR_UDRDY_Pos (18U)
10753#define PWR_CSR_UDRDY_Msk (0x3UL << PWR_CSR_UDRDY_Pos)
10754#define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk
10755/* Legacy define */
10756#define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
10757
10758/* Legacy define */
10759#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
10760
10761/******************************************************************************/
10762/* */
10763/* Reset and Clock Control */
10764/* */
10765/******************************************************************************/
10766/******************** Bit definition for RCC_CR register ********************/
10767#define RCC_CR_HSION_Pos (0U)
10768#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
10769#define RCC_CR_HSION RCC_CR_HSION_Msk
10770#define RCC_CR_HSIRDY_Pos (1U)
10771#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
10772#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
10773
10774#define RCC_CR_HSITRIM_Pos (3U)
10775#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
10776#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
10777#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
10778#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
10779#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
10780#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
10781#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
10782
10783#define RCC_CR_HSICAL_Pos (8U)
10784#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
10785#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
10786#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
10787#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
10788#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
10789#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
10790#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
10791#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
10792#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
10793#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
10794
10795#define RCC_CR_HSEON_Pos (16U)
10796#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
10797#define RCC_CR_HSEON RCC_CR_HSEON_Msk
10798#define RCC_CR_HSERDY_Pos (17U)
10799#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
10800#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
10801#define RCC_CR_HSEBYP_Pos (18U)
10802#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
10803#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
10804#define RCC_CR_CSSON_Pos (19U)
10805#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
10806#define RCC_CR_CSSON RCC_CR_CSSON_Msk
10807#define RCC_CR_PLLON_Pos (24U)
10808#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
10809#define RCC_CR_PLLON RCC_CR_PLLON_Msk
10810#define RCC_CR_PLLRDY_Pos (25U)
10811#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
10812#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
10813/*
10814 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
10815 */
10816#define RCC_PLLI2S_SUPPORT
10817
10818#define RCC_CR_PLLI2SON_Pos (26U)
10819#define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)
10820#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
10821#define RCC_CR_PLLI2SRDY_Pos (27U)
10822#define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)
10823#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
10824/*
10825 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
10826 */
10827#define RCC_PLLSAI_SUPPORT
10828
10829#define RCC_CR_PLLSAION_Pos (28U)
10830#define RCC_CR_PLLSAION_Msk (0x1UL << RCC_CR_PLLSAION_Pos)
10831#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
10832#define RCC_CR_PLLSAIRDY_Pos (29U)
10833#define RCC_CR_PLLSAIRDY_Msk (0x1UL << RCC_CR_PLLSAIRDY_Pos)
10834#define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
10835
10836/******************** Bit definition for RCC_PLLCFGR register ***************/
10837#define RCC_PLLCFGR_PLLM_Pos (0U)
10838#define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
10839#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
10840#define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)
10841#define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)
10842#define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)
10843#define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)
10844#define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)
10845#define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)
10846
10847#define RCC_PLLCFGR_PLLN_Pos (6U)
10848#define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
10849#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
10850#define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)
10851#define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)
10852#define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)
10853#define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)
10854#define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)
10855#define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)
10856#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)
10857#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)
10858#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)
10859
10860#define RCC_PLLCFGR_PLLP_Pos (16U)
10861#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)
10862#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
10863#define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)
10864#define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)
10865
10866#define RCC_PLLCFGR_PLLSRC_Pos (22U)
10867#define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
10868#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
10869#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
10870#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
10871#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
10872#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
10873
10874#define RCC_PLLCFGR_PLLQ_Pos (24U)
10875#define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
10876#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
10877#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
10878#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
10879#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
10880#define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
10881
10882
10883/******************** Bit definition for RCC_CFGR register ******************/
10885#define RCC_CFGR_SW_Pos (0U)
10886#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
10887#define RCC_CFGR_SW RCC_CFGR_SW_Msk
10888#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
10889#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
10890
10891#define RCC_CFGR_SW_HSI 0x00000000U
10892#define RCC_CFGR_SW_HSE 0x00000001U
10893#define RCC_CFGR_SW_PLL 0x00000002U
10894
10896#define RCC_CFGR_SWS_Pos (2U)
10897#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
10898#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
10899#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
10900#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
10901
10902#define RCC_CFGR_SWS_HSI 0x00000000U
10903#define RCC_CFGR_SWS_HSE 0x00000004U
10904#define RCC_CFGR_SWS_PLL 0x00000008U
10905
10907#define RCC_CFGR_HPRE_Pos (4U)
10908#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
10909#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
10910#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
10911#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
10912#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
10913#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
10914
10915#define RCC_CFGR_HPRE_DIV1 0x00000000U
10916#define RCC_CFGR_HPRE_DIV2 0x00000080U
10917#define RCC_CFGR_HPRE_DIV4 0x00000090U
10918#define RCC_CFGR_HPRE_DIV8 0x000000A0U
10919#define RCC_CFGR_HPRE_DIV16 0x000000B0U
10920#define RCC_CFGR_HPRE_DIV64 0x000000C0U
10921#define RCC_CFGR_HPRE_DIV128 0x000000D0U
10922#define RCC_CFGR_HPRE_DIV256 0x000000E0U
10923#define RCC_CFGR_HPRE_DIV512 0x000000F0U
10924
10926#define RCC_CFGR_PPRE1_Pos (10U)
10927#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
10928#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
10929#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
10930#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
10931#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
10932
10933#define RCC_CFGR_PPRE1_DIV1 0x00000000U
10934#define RCC_CFGR_PPRE1_DIV2 0x00001000U
10935#define RCC_CFGR_PPRE1_DIV4 0x00001400U
10936#define RCC_CFGR_PPRE1_DIV8 0x00001800U
10937#define RCC_CFGR_PPRE1_DIV16 0x00001C00U
10938
10940#define RCC_CFGR_PPRE2_Pos (13U)
10941#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
10942#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
10943#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
10944#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
10945#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
10946
10947#define RCC_CFGR_PPRE2_DIV1 0x00000000U
10948#define RCC_CFGR_PPRE2_DIV2 0x00008000U
10949#define RCC_CFGR_PPRE2_DIV4 0x0000A000U
10950#define RCC_CFGR_PPRE2_DIV8 0x0000C000U
10951#define RCC_CFGR_PPRE2_DIV16 0x0000E000U
10952
10954#define RCC_CFGR_RTCPRE_Pos (16U)
10955#define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)
10956#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
10957#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)
10958#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)
10959#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)
10960#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)
10961#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
10962
10964#define RCC_CFGR_MCO1_Pos (21U)
10965#define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)
10966#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
10967#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
10968#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
10969
10970#define RCC_CFGR_I2SSRC_Pos (23U)
10971#define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)
10972#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
10973
10974#define RCC_CFGR_MCO1PRE_Pos (24U)
10975#define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)
10976#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
10977#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
10978#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
10979#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
10980
10981#define RCC_CFGR_MCO2PRE_Pos (27U)
10982#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)
10983#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
10984#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
10985#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
10986#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
10987
10988#define RCC_CFGR_MCO2_Pos (30U)
10989#define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)
10990#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
10991#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
10992#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
10993
10994/******************** Bit definition for RCC_CIR register *******************/
10995#define RCC_CIR_LSIRDYF_Pos (0U)
10996#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
10997#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
10998#define RCC_CIR_LSERDYF_Pos (1U)
10999#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
11000#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
11001#define RCC_CIR_HSIRDYF_Pos (2U)
11002#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
11003#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
11004#define RCC_CIR_HSERDYF_Pos (3U)
11005#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
11006#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
11007#define RCC_CIR_PLLRDYF_Pos (4U)
11008#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
11009#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
11010#define RCC_CIR_PLLI2SRDYF_Pos (5U)
11011#define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
11012#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
11013
11014#define RCC_CIR_PLLSAIRDYF_Pos (6U)
11015#define RCC_CIR_PLLSAIRDYF_Msk (0x1UL << RCC_CIR_PLLSAIRDYF_Pos)
11016#define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
11017#define RCC_CIR_CSSF_Pos (7U)
11018#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
11019#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
11020#define RCC_CIR_LSIRDYIE_Pos (8U)
11021#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
11022#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
11023#define RCC_CIR_LSERDYIE_Pos (9U)
11024#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
11025#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
11026#define RCC_CIR_HSIRDYIE_Pos (10U)
11027#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
11028#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
11029#define RCC_CIR_HSERDYIE_Pos (11U)
11030#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
11031#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
11032#define RCC_CIR_PLLRDYIE_Pos (12U)
11033#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
11034#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
11035#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
11036#define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
11037#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
11038
11039#define RCC_CIR_PLLSAIRDYIE_Pos (14U)
11040#define RCC_CIR_PLLSAIRDYIE_Msk (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos)
11041#define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
11042#define RCC_CIR_LSIRDYC_Pos (16U)
11043#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
11044#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
11045#define RCC_CIR_LSERDYC_Pos (17U)
11046#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
11047#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
11048#define RCC_CIR_HSIRDYC_Pos (18U)
11049#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
11050#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
11051#define RCC_CIR_HSERDYC_Pos (19U)
11052#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
11053#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
11054#define RCC_CIR_PLLRDYC_Pos (20U)
11055#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
11056#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
11057#define RCC_CIR_PLLI2SRDYC_Pos (21U)
11058#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
11059#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
11060#define RCC_CIR_PLLSAIRDYC_Pos (22U)
11061#define RCC_CIR_PLLSAIRDYC_Msk (0x1UL << RCC_CIR_PLLSAIRDYC_Pos)
11062#define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
11063
11064#define RCC_CIR_CSSC_Pos (23U)
11065#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
11066#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
11067
11068/******************** Bit definition for RCC_AHB1RSTR register **************/
11069#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
11070#define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
11071#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
11072#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
11073#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
11074#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
11075#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
11076#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
11077#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
11078#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
11079#define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
11080#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
11081#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
11082#define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
11083#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
11084#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
11085#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
11086#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
11087#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
11088#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
11089#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
11090#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
11091#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
11092#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
11093#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
11094#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos)
11095#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
11096#define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
11097#define RCC_AHB1RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOJRST_Pos)
11098#define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
11099#define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
11100#define RCC_AHB1RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOKRST_Pos)
11101#define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
11102#define RCC_AHB1RSTR_CRCRST_Pos (12U)
11103#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
11104#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
11105#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
11106#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
11107#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
11108#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
11109#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
11110#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
11111#define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
11112#define RCC_AHB1RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos)
11113#define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
11114#define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
11115#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos)
11116#define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
11117#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
11118#define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)
11119#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
11120
11121/******************** Bit definition for RCC_AHB2RSTR register **************/
11122#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
11123#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
11124#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
11125#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
11126#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)
11127#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
11128#define RCC_AHB2RSTR_HASHRST_Pos (5U)
11129#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)
11130#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
11131/* maintained for legacy purpose */
11132#define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
11133#define RCC_AHB2RSTR_RNGRST_Pos (6U)
11134#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
11135#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
11136#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
11137#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
11138#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
11139/******************** Bit definition for RCC_AHB3RSTR register **************/
11140#define RCC_AHB3RSTR_FMCRST_Pos (0U)
11141#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
11142#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
11143
11144
11145/******************** Bit definition for RCC_APB1RSTR register **************/
11146#define RCC_APB1RSTR_TIM2RST_Pos (0U)
11147#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
11148#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
11149#define RCC_APB1RSTR_TIM3RST_Pos (1U)
11150#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
11151#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
11152#define RCC_APB1RSTR_TIM4RST_Pos (2U)
11153#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
11154#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
11155#define RCC_APB1RSTR_TIM5RST_Pos (3U)
11156#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
11157#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
11158#define RCC_APB1RSTR_TIM6RST_Pos (4U)
11159#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
11160#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
11161#define RCC_APB1RSTR_TIM7RST_Pos (5U)
11162#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
11163#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
11164#define RCC_APB1RSTR_TIM12RST_Pos (6U)
11165#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
11166#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
11167#define RCC_APB1RSTR_TIM13RST_Pos (7U)
11168#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
11169#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
11170#define RCC_APB1RSTR_TIM14RST_Pos (8U)
11171#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
11172#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
11173#define RCC_APB1RSTR_WWDGRST_Pos (11U)
11174#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
11175#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
11176#define RCC_APB1RSTR_SPI2RST_Pos (14U)
11177#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
11178#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
11179#define RCC_APB1RSTR_SPI3RST_Pos (15U)
11180#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
11181#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
11182#define RCC_APB1RSTR_USART2RST_Pos (17U)
11183#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
11184#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
11185#define RCC_APB1RSTR_USART3RST_Pos (18U)
11186#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
11187#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
11188#define RCC_APB1RSTR_UART4RST_Pos (19U)
11189#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
11190#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
11191#define RCC_APB1RSTR_UART5RST_Pos (20U)
11192#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
11193#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
11194#define RCC_APB1RSTR_I2C1RST_Pos (21U)
11195#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
11196#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
11197#define RCC_APB1RSTR_I2C2RST_Pos (22U)
11198#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
11199#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
11200#define RCC_APB1RSTR_I2C3RST_Pos (23U)
11201#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
11202#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
11203#define RCC_APB1RSTR_CAN1RST_Pos (25U)
11204#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
11205#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
11206#define RCC_APB1RSTR_CAN2RST_Pos (26U)
11207#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
11208#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
11209#define RCC_APB1RSTR_PWRRST_Pos (28U)
11210#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
11211#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
11212#define RCC_APB1RSTR_DACRST_Pos (29U)
11213#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)
11214#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
11215#define RCC_APB1RSTR_UART7RST_Pos (30U)
11216#define RCC_APB1RSTR_UART7RST_Msk (0x1UL << RCC_APB1RSTR_UART7RST_Pos)
11217#define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
11218#define RCC_APB1RSTR_UART8RST_Pos (31U)
11219#define RCC_APB1RSTR_UART8RST_Msk (0x1UL << RCC_APB1RSTR_UART8RST_Pos)
11220#define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
11221
11222/******************** Bit definition for RCC_APB2RSTR register **************/
11223#define RCC_APB2RSTR_TIM1RST_Pos (0U)
11224#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
11225#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
11226#define RCC_APB2RSTR_TIM8RST_Pos (1U)
11227#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
11228#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
11229#define RCC_APB2RSTR_USART1RST_Pos (4U)
11230#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
11231#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
11232#define RCC_APB2RSTR_USART6RST_Pos (5U)
11233#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
11234#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
11235#define RCC_APB2RSTR_ADCRST_Pos (8U)
11236#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
11237#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
11238#define RCC_APB2RSTR_SDIORST_Pos (11U)
11239#define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos)
11240#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
11241#define RCC_APB2RSTR_SPI1RST_Pos (12U)
11242#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
11243#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
11244#define RCC_APB2RSTR_SPI4RST_Pos (13U)
11245#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
11246#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
11247#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
11248#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
11249#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
11250#define RCC_APB2RSTR_TIM9RST_Pos (16U)
11251#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
11252#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
11253#define RCC_APB2RSTR_TIM10RST_Pos (17U)
11254#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
11255#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
11256#define RCC_APB2RSTR_TIM11RST_Pos (18U)
11257#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
11258#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
11259#define RCC_APB2RSTR_SPI5RST_Pos (20U)
11260#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)
11261#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
11262#define RCC_APB2RSTR_SPI6RST_Pos (21U)
11263#define RCC_APB2RSTR_SPI6RST_Msk (0x1UL << RCC_APB2RSTR_SPI6RST_Pos)
11264#define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
11265#define RCC_APB2RSTR_SAI1RST_Pos (22U)
11266#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
11267#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
11268#define RCC_APB2RSTR_LTDCRST_Pos (26U)
11269#define RCC_APB2RSTR_LTDCRST_Msk (0x1UL << RCC_APB2RSTR_LTDCRST_Pos)
11270#define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
11271
11272/* Old SPI1RST bit definition, maintained for legacy purpose */
11273#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
11274
11275/******************** Bit definition for RCC_AHB1ENR register ***************/
11276#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
11277#define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
11278#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
11279#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
11280#define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
11281#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
11282#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
11283#define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
11284#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
11285#define RCC_AHB1ENR_GPIODEN_Pos (3U)
11286#define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
11287#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
11288#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
11289#define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
11290#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
11291#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
11292#define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
11293#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
11294#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
11295#define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
11296#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
11297#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
11298#define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
11299#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
11300#define RCC_AHB1ENR_GPIOIEN_Pos (8U)
11301#define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)
11302#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
11303#define RCC_AHB1ENR_GPIOJEN_Pos (9U)
11304#define RCC_AHB1ENR_GPIOJEN_Msk (0x1UL << RCC_AHB1ENR_GPIOJEN_Pos)
11305#define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
11306#define RCC_AHB1ENR_GPIOKEN_Pos (10U)
11307#define RCC_AHB1ENR_GPIOKEN_Msk (0x1UL << RCC_AHB1ENR_GPIOKEN_Pos)
11308#define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
11309#define RCC_AHB1ENR_CRCEN_Pos (12U)
11310#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
11311#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
11312#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
11313#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)
11314#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
11315#define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
11316#define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos)
11317#define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
11318#define RCC_AHB1ENR_DMA1EN_Pos (21U)
11319#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
11320#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
11321#define RCC_AHB1ENR_DMA2EN_Pos (22U)
11322#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
11323#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
11324#define RCC_AHB1ENR_DMA2DEN_Pos (23U)
11325#define RCC_AHB1ENR_DMA2DEN_Msk (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos)
11326#define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
11327#define RCC_AHB1ENR_ETHMACEN_Pos (25U)
11328#define RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)
11329#define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
11330#define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
11331#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos)
11332#define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
11333#define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
11334#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos)
11335#define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
11336#define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
11337#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos)
11338#define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
11339#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
11340#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)
11341#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
11342#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
11343#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)
11344#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
11345/******************** Bit definition for RCC_AHB2ENR register ***************/
11346/*
11347 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
11348 */
11349#define RCC_AHB2_SUPPORT
11350
11351#define RCC_AHB2ENR_DCMIEN_Pos (0U)
11352#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
11353#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
11354#define RCC_AHB2ENR_CRYPEN_Pos (4U)
11355#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)
11356#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
11357#define RCC_AHB2ENR_HASHEN_Pos (5U)
11358#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos)
11359#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
11360#define RCC_AHB2ENR_RNGEN_Pos (6U)
11361#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
11362#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
11363#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
11364#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
11365#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
11366
11367/******************** Bit definition for RCC_AHB3ENR register ***************/
11368/*
11369 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
11370 */
11371#define RCC_AHB3_SUPPORT
11372
11373#define RCC_AHB3ENR_FMCEN_Pos (0U)
11374#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
11375#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
11376
11377/******************** Bit definition for RCC_APB1ENR register ***************/
11378#define RCC_APB1ENR_TIM2EN_Pos (0U)
11379#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
11380#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
11381#define RCC_APB1ENR_TIM3EN_Pos (1U)
11382#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
11383#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
11384#define RCC_APB1ENR_TIM4EN_Pos (2U)
11385#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
11386#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
11387#define RCC_APB1ENR_TIM5EN_Pos (3U)
11388#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
11389#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
11390#define RCC_APB1ENR_TIM6EN_Pos (4U)
11391#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
11392#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
11393#define RCC_APB1ENR_TIM7EN_Pos (5U)
11394#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
11395#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
11396#define RCC_APB1ENR_TIM12EN_Pos (6U)
11397#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
11398#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
11399#define RCC_APB1ENR_TIM13EN_Pos (7U)
11400#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
11401#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
11402#define RCC_APB1ENR_TIM14EN_Pos (8U)
11403#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
11404#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
11405#define RCC_APB1ENR_WWDGEN_Pos (11U)
11406#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
11407#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
11408#define RCC_APB1ENR_SPI2EN_Pos (14U)
11409#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
11410#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
11411#define RCC_APB1ENR_SPI3EN_Pos (15U)
11412#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
11413#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
11414#define RCC_APB1ENR_USART2EN_Pos (17U)
11415#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
11416#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
11417#define RCC_APB1ENR_USART3EN_Pos (18U)
11418#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
11419#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
11420#define RCC_APB1ENR_UART4EN_Pos (19U)
11421#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
11422#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
11423#define RCC_APB1ENR_UART5EN_Pos (20U)
11424#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
11425#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
11426#define RCC_APB1ENR_I2C1EN_Pos (21U)
11427#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
11428#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
11429#define RCC_APB1ENR_I2C2EN_Pos (22U)
11430#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
11431#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
11432#define RCC_APB1ENR_I2C3EN_Pos (23U)
11433#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
11434#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
11435#define RCC_APB1ENR_CAN1EN_Pos (25U)
11436#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
11437#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
11438#define RCC_APB1ENR_CAN2EN_Pos (26U)
11439#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
11440#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
11441#define RCC_APB1ENR_PWREN_Pos (28U)
11442#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
11443#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
11444#define RCC_APB1ENR_DACEN_Pos (29U)
11445#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)
11446#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
11447#define RCC_APB1ENR_UART7EN_Pos (30U)
11448#define RCC_APB1ENR_UART7EN_Msk (0x1UL << RCC_APB1ENR_UART7EN_Pos)
11449#define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
11450#define RCC_APB1ENR_UART8EN_Pos (31U)
11451#define RCC_APB1ENR_UART8EN_Msk (0x1UL << RCC_APB1ENR_UART8EN_Pos)
11452#define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
11453
11454/******************** Bit definition for RCC_APB2ENR register ***************/
11455#define RCC_APB2ENR_TIM1EN_Pos (0U)
11456#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
11457#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
11458#define RCC_APB2ENR_TIM8EN_Pos (1U)
11459#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
11460#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
11461#define RCC_APB2ENR_USART1EN_Pos (4U)
11462#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
11463#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
11464#define RCC_APB2ENR_USART6EN_Pos (5U)
11465#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
11466#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
11467#define RCC_APB2ENR_ADC1EN_Pos (8U)
11468#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
11469#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
11470#define RCC_APB2ENR_ADC2EN_Pos (9U)
11471#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
11472#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
11473#define RCC_APB2ENR_ADC3EN_Pos (10U)
11474#define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos)
11475#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
11476#define RCC_APB2ENR_SDIOEN_Pos (11U)
11477#define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos)
11478#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
11479#define RCC_APB2ENR_SPI1EN_Pos (12U)
11480#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
11481#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
11482#define RCC_APB2ENR_SPI4EN_Pos (13U)
11483#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
11484#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
11485#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
11486#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
11487#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
11488#define RCC_APB2ENR_TIM9EN_Pos (16U)
11489#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
11490#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
11491#define RCC_APB2ENR_TIM10EN_Pos (17U)
11492#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
11493#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
11494#define RCC_APB2ENR_TIM11EN_Pos (18U)
11495#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
11496#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
11497#define RCC_APB2ENR_SPI5EN_Pos (20U)
11498#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos)
11499#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
11500#define RCC_APB2ENR_SPI6EN_Pos (21U)
11501#define RCC_APB2ENR_SPI6EN_Msk (0x1UL << RCC_APB2ENR_SPI6EN_Pos)
11502#define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
11503#define RCC_APB2ENR_SAI1EN_Pos (22U)
11504#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
11505#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
11506#define RCC_APB2ENR_LTDCEN_Pos (26U)
11507#define RCC_APB2ENR_LTDCEN_Msk (0x1UL << RCC_APB2ENR_LTDCEN_Pos)
11508#define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
11509
11510/******************** Bit definition for RCC_AHB1LPENR register *************/
11511#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
11512#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
11513#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
11514#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
11515#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
11516#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
11517#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
11518#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
11519#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
11520#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
11521#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
11522#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
11523#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
11524#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
11525#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
11526#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
11527#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
11528#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
11529#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
11530#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
11531#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
11532#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
11533#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
11534#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
11535#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
11536#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos)
11537#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
11538#define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
11539#define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOJLPEN_Pos)
11540#define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
11541#define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
11542#define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOKLPEN_Pos)
11543#define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
11544#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
11545#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
11546#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
11547#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
11548#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
11549#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
11550#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
11551#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
11552#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
11553#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
11554#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
11555#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
11556#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
11557#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)
11558#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
11559#define RCC_AHB1LPENR_SRAM3LPEN_Pos (19U)
11560#define RCC_AHB1LPENR_SRAM3LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM3LPEN_Pos)
11561#define RCC_AHB1LPENR_SRAM3LPEN RCC_AHB1LPENR_SRAM3LPEN_Msk
11562#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
11563#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
11564#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
11565#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
11566#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
11567#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
11568#define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
11569#define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2DLPEN_Pos)
11570#define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
11571
11572#define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
11573#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos)
11574#define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
11575#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
11576#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos)
11577#define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
11578#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
11579#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos)
11580#define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
11581#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
11582#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos)
11583#define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
11584#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
11585#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)
11586#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
11587#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
11588#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)
11589#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
11590
11591/******************** Bit definition for RCC_AHB2LPENR register *************/
11592#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
11593#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)
11594#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
11595#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
11596#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos)
11597#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
11598#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
11599#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos)
11600#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
11601#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
11602#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
11603#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
11604#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
11605#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
11606#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
11607
11608/******************** Bit definition for RCC_AHB3LPENR register *************/
11609#define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
11610#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)
11611#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
11612
11613/******************** Bit definition for RCC_APB1LPENR register *************/
11614#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
11615#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
11616#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
11617#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
11618#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
11619#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
11620#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
11621#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
11622#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
11623#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
11624#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
11625#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
11626#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
11627#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
11628#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
11629#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
11630#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
11631#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
11632#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
11633#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
11634#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
11635#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
11636#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
11637#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
11638#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
11639#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
11640#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
11641#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
11642#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
11643#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
11644#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
11645#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
11646#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
11647#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
11648#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
11649#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
11650#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
11651#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
11652#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
11653#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
11654#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
11655#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
11656#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
11657#define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
11658#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
11659#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
11660#define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
11661#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
11662#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
11663#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
11664#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
11665#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
11666#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
11667#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
11668#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
11669#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
11670#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
11671#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
11672#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
11673#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
11674#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
11675#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
11676#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
11677#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
11678#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
11679#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
11680#define RCC_APB1LPENR_DACLPEN_Pos (29U)
11681#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
11682#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
11683#define RCC_APB1LPENR_UART7LPEN_Pos (30U)
11684#define RCC_APB1LPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos)
11685#define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
11686#define RCC_APB1LPENR_UART8LPEN_Pos (31U)
11687#define RCC_APB1LPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos)
11688#define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
11689
11690/******************** Bit definition for RCC_APB2LPENR register *************/
11691#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
11692#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
11693#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
11694#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
11695#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
11696#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
11697#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
11698#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
11699#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
11700#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
11701#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
11702#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
11703#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
11704#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
11705#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
11706#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
11707#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)
11708#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
11709#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
11710#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)
11711#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
11712#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
11713#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)
11714#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
11715#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
11716#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
11717#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
11718#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
11719#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
11720#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
11721#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
11722#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
11723#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
11724#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
11725#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
11726#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
11727#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
11728#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
11729#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
11730#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
11731#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
11732#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
11733#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
11734#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)
11735#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
11736#define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
11737#define RCC_APB2LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI6LPEN_Pos)
11738#define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
11739#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
11740#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)
11741#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
11742#define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
11743#define RCC_APB2LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB2LPENR_LTDCLPEN_Pos)
11744#define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
11745
11746/******************** Bit definition for RCC_BDCR register ******************/
11747#define RCC_BDCR_LSEON_Pos (0U)
11748#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
11749#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
11750#define RCC_BDCR_LSERDY_Pos (1U)
11751#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
11752#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
11753#define RCC_BDCR_LSEBYP_Pos (2U)
11754#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
11755#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
11756
11757#define RCC_BDCR_RTCSEL_Pos (8U)
11758#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
11759#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
11760#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
11761#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
11762
11763#define RCC_BDCR_RTCEN_Pos (15U)
11764#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
11765#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
11766#define RCC_BDCR_BDRST_Pos (16U)
11767#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
11768#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
11769
11770/******************** Bit definition for RCC_CSR register *******************/
11771#define RCC_CSR_LSION_Pos (0U)
11772#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
11773#define RCC_CSR_LSION RCC_CSR_LSION_Msk
11774#define RCC_CSR_LSIRDY_Pos (1U)
11775#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
11776#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
11777#define RCC_CSR_RMVF_Pos (24U)
11778#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
11779#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
11780#define RCC_CSR_BORRSTF_Pos (25U)
11781#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
11782#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
11783#define RCC_CSR_PINRSTF_Pos (26U)
11784#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
11785#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
11786#define RCC_CSR_PORRSTF_Pos (27U)
11787#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
11788#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
11789#define RCC_CSR_SFTRSTF_Pos (28U)
11790#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
11791#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
11792#define RCC_CSR_IWDGRSTF_Pos (29U)
11793#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
11794#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
11795#define RCC_CSR_WWDGRSTF_Pos (30U)
11796#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
11797#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
11798#define RCC_CSR_LPWRRSTF_Pos (31U)
11799#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
11800#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
11801/* Legacy defines */
11802#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
11803#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
11804
11805/******************** Bit definition for RCC_SSCGR register *****************/
11806#define RCC_SSCGR_MODPER_Pos (0U)
11807#define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
11808#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
11809#define RCC_SSCGR_INCSTEP_Pos (13U)
11810#define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
11811#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
11812#define RCC_SSCGR_SPREADSEL_Pos (30U)
11813#define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
11814#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
11815#define RCC_SSCGR_SSCGEN_Pos (31U)
11816#define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)
11817#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
11818
11819/******************** Bit definition for RCC_PLLI2SCFGR register ************/
11820#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
11821#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11822#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
11823#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11824#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11825#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11826#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11827#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11828#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11829#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11830#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11831#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11832
11833#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
11834#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11835#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
11836#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11837#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11838#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11839#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11840#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
11841#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
11842#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
11843#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
11844#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
11845#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
11846
11847/******************** Bit definition for RCC_PLLSAICFGR register ************/
11848#define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
11849#define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11850#define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
11851#define RCC_PLLSAICFGR_PLLSAIN_0 (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11852#define RCC_PLLSAICFGR_PLLSAIN_1 (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11853#define RCC_PLLSAICFGR_PLLSAIN_2 (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11854#define RCC_PLLSAICFGR_PLLSAIN_3 (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11855#define RCC_PLLSAICFGR_PLLSAIN_4 (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11856#define RCC_PLLSAICFGR_PLLSAIN_5 (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11857#define RCC_PLLSAICFGR_PLLSAIN_6 (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11858#define RCC_PLLSAICFGR_PLLSAIN_7 (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11859#define RCC_PLLSAICFGR_PLLSAIN_8 (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11860
11861
11862#define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
11863#define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11864#define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
11865#define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11866#define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11867#define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11868#define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11869
11870#define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
11871#define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
11872#define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
11873#define RCC_PLLSAICFGR_PLLSAIR_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
11874#define RCC_PLLSAICFGR_PLLSAIR_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
11875#define RCC_PLLSAICFGR_PLLSAIR_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
11876
11877/******************** Bit definition for RCC_DCKCFGR register ***************/
11878#define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
11879#define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FUL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
11880#define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
11881#define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
11882#define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
11883#define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
11884#define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
11885#define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
11886
11887#define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
11888#define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FUL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
11889#define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
11890#define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
11891#define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
11892#define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
11893#define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
11894#define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
11895#define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
11896#define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR_PLLSAIDIVR_Pos)
11897#define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
11898#define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR_PLLSAIDIVR_Pos)
11899#define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR_PLLSAIDIVR_Pos)
11900
11901#define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
11902#define RCC_DCKCFGR_SAI1ASRC_Msk (0x3UL << RCC_DCKCFGR_SAI1ASRC_Pos)
11903#define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
11904#define RCC_DCKCFGR_SAI1ASRC_0 (0x1UL << RCC_DCKCFGR_SAI1ASRC_Pos)
11905#define RCC_DCKCFGR_SAI1ASRC_1 (0x2UL << RCC_DCKCFGR_SAI1ASRC_Pos)
11906#define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
11907#define RCC_DCKCFGR_SAI1BSRC_Msk (0x3UL << RCC_DCKCFGR_SAI1BSRC_Pos)
11908#define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
11909#define RCC_DCKCFGR_SAI1BSRC_0 (0x1UL << RCC_DCKCFGR_SAI1BSRC_Pos)
11910#define RCC_DCKCFGR_SAI1BSRC_1 (0x2UL << RCC_DCKCFGR_SAI1BSRC_Pos)
11911#define RCC_DCKCFGR_TIMPRE_Pos (24U)
11912#define RCC_DCKCFGR_TIMPRE_Msk (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)
11913#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
11914
11915
11916/******************************************************************************/
11917/* */
11918/* RNG */
11919/* */
11920/******************************************************************************/
11921/******************** Bits definition for RNG_CR register *******************/
11922#define RNG_CR_RNGEN_Pos (2U)
11923#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
11924#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
11925#define RNG_CR_IE_Pos (3U)
11926#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
11927#define RNG_CR_IE RNG_CR_IE_Msk
11928
11929/******************** Bits definition for RNG_SR register *******************/
11930#define RNG_SR_DRDY_Pos (0U)
11931#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
11932#define RNG_SR_DRDY RNG_SR_DRDY_Msk
11933#define RNG_SR_CECS_Pos (1U)
11934#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
11935#define RNG_SR_CECS RNG_SR_CECS_Msk
11936#define RNG_SR_SECS_Pos (2U)
11937#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
11938#define RNG_SR_SECS RNG_SR_SECS_Msk
11939#define RNG_SR_CEIS_Pos (5U)
11940#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
11941#define RNG_SR_CEIS RNG_SR_CEIS_Msk
11942#define RNG_SR_SEIS_Pos (6U)
11943#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
11944#define RNG_SR_SEIS RNG_SR_SEIS_Msk
11945
11946/******************************************************************************/
11947/* */
11948/* Real-Time Clock (RTC) */
11949/* */
11950/******************************************************************************/
11951/*
11952 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
11953 */
11954#define RTC_TAMPER2_SUPPORT
11955#define RTC_AF2_SUPPORT
11956/******************** Bits definition for RTC_TR register *******************/
11957#define RTC_TR_PM_Pos (22U)
11958#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
11959#define RTC_TR_PM RTC_TR_PM_Msk
11960#define RTC_TR_HT_Pos (20U)
11961#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
11962#define RTC_TR_HT RTC_TR_HT_Msk
11963#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
11964#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
11965#define RTC_TR_HU_Pos (16U)
11966#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
11967#define RTC_TR_HU RTC_TR_HU_Msk
11968#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
11969#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
11970#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
11971#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
11972#define RTC_TR_MNT_Pos (12U)
11973#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
11974#define RTC_TR_MNT RTC_TR_MNT_Msk
11975#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
11976#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
11977#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
11978#define RTC_TR_MNU_Pos (8U)
11979#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
11980#define RTC_TR_MNU RTC_TR_MNU_Msk
11981#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
11982#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
11983#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
11984#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
11985#define RTC_TR_ST_Pos (4U)
11986#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
11987#define RTC_TR_ST RTC_TR_ST_Msk
11988#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
11989#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
11990#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
11991#define RTC_TR_SU_Pos (0U)
11992#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
11993#define RTC_TR_SU RTC_TR_SU_Msk
11994#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
11995#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
11996#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
11997#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
11998
11999/******************** Bits definition for RTC_DR register *******************/
12000#define RTC_DR_YT_Pos (20U)
12001#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
12002#define RTC_DR_YT RTC_DR_YT_Msk
12003#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
12004#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
12005#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
12006#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
12007#define RTC_DR_YU_Pos (16U)
12008#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
12009#define RTC_DR_YU RTC_DR_YU_Msk
12010#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
12011#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
12012#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
12013#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
12014#define RTC_DR_WDU_Pos (13U)
12015#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
12016#define RTC_DR_WDU RTC_DR_WDU_Msk
12017#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
12018#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
12019#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
12020#define RTC_DR_MT_Pos (12U)
12021#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
12022#define RTC_DR_MT RTC_DR_MT_Msk
12023#define RTC_DR_MU_Pos (8U)
12024#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
12025#define RTC_DR_MU RTC_DR_MU_Msk
12026#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
12027#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
12028#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
12029#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
12030#define RTC_DR_DT_Pos (4U)
12031#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
12032#define RTC_DR_DT RTC_DR_DT_Msk
12033#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
12034#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
12035#define RTC_DR_DU_Pos (0U)
12036#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
12037#define RTC_DR_DU RTC_DR_DU_Msk
12038#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
12039#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
12040#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
12041#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
12042
12043/******************** Bits definition for RTC_CR register *******************/
12044#define RTC_CR_COE_Pos (23U)
12045#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
12046#define RTC_CR_COE RTC_CR_COE_Msk
12047#define RTC_CR_OSEL_Pos (21U)
12048#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
12049#define RTC_CR_OSEL RTC_CR_OSEL_Msk
12050#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
12051#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
12052#define RTC_CR_POL_Pos (20U)
12053#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
12054#define RTC_CR_POL RTC_CR_POL_Msk
12055#define RTC_CR_COSEL_Pos (19U)
12056#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
12057#define RTC_CR_COSEL RTC_CR_COSEL_Msk
12058#define RTC_CR_BKP_Pos (18U)
12059#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
12060#define RTC_CR_BKP RTC_CR_BKP_Msk
12061#define RTC_CR_SUB1H_Pos (17U)
12062#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
12063#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
12064#define RTC_CR_ADD1H_Pos (16U)
12065#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
12066#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
12067#define RTC_CR_TSIE_Pos (15U)
12068#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
12069#define RTC_CR_TSIE RTC_CR_TSIE_Msk
12070#define RTC_CR_WUTIE_Pos (14U)
12071#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
12072#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
12073#define RTC_CR_ALRBIE_Pos (13U)
12074#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
12075#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
12076#define RTC_CR_ALRAIE_Pos (12U)
12077#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
12078#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
12079#define RTC_CR_TSE_Pos (11U)
12080#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
12081#define RTC_CR_TSE RTC_CR_TSE_Msk
12082#define RTC_CR_WUTE_Pos (10U)
12083#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
12084#define RTC_CR_WUTE RTC_CR_WUTE_Msk
12085#define RTC_CR_ALRBE_Pos (9U)
12086#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
12087#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
12088#define RTC_CR_ALRAE_Pos (8U)
12089#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
12090#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
12091#define RTC_CR_DCE_Pos (7U)
12092#define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos)
12093#define RTC_CR_DCE RTC_CR_DCE_Msk
12094#define RTC_CR_FMT_Pos (6U)
12095#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
12096#define RTC_CR_FMT RTC_CR_FMT_Msk
12097#define RTC_CR_BYPSHAD_Pos (5U)
12098#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
12099#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
12100#define RTC_CR_REFCKON_Pos (4U)
12101#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
12102#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
12103#define RTC_CR_TSEDGE_Pos (3U)
12104#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
12105#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
12106#define RTC_CR_WUCKSEL_Pos (0U)
12107#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
12108#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
12109#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
12110#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
12111#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
12112
12113/* Legacy defines */
12114#define RTC_CR_BCK RTC_CR_BKP
12115
12116/******************** Bits definition for RTC_ISR register ******************/
12117#define RTC_ISR_RECALPF_Pos (16U)
12118#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
12119#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
12120#define RTC_ISR_TAMP1F_Pos (13U)
12121#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
12122#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
12123#define RTC_ISR_TAMP2F_Pos (14U)
12124#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
12125#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
12126#define RTC_ISR_TSOVF_Pos (12U)
12127#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
12128#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
12129#define RTC_ISR_TSF_Pos (11U)
12130#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
12131#define RTC_ISR_TSF RTC_ISR_TSF_Msk
12132#define RTC_ISR_WUTF_Pos (10U)
12133#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
12134#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
12135#define RTC_ISR_ALRBF_Pos (9U)
12136#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
12137#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
12138#define RTC_ISR_ALRAF_Pos (8U)
12139#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
12140#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
12141#define RTC_ISR_INIT_Pos (7U)
12142#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
12143#define RTC_ISR_INIT RTC_ISR_INIT_Msk
12144#define RTC_ISR_INITF_Pos (6U)
12145#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
12146#define RTC_ISR_INITF RTC_ISR_INITF_Msk
12147#define RTC_ISR_RSF_Pos (5U)
12148#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
12149#define RTC_ISR_RSF RTC_ISR_RSF_Msk
12150#define RTC_ISR_INITS_Pos (4U)
12151#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
12152#define RTC_ISR_INITS RTC_ISR_INITS_Msk
12153#define RTC_ISR_SHPF_Pos (3U)
12154#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
12155#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
12156#define RTC_ISR_WUTWF_Pos (2U)
12157#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
12158#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
12159#define RTC_ISR_ALRBWF_Pos (1U)
12160#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
12161#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
12162#define RTC_ISR_ALRAWF_Pos (0U)
12163#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
12164#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
12165
12166/******************** Bits definition for RTC_PRER register *****************/
12167#define RTC_PRER_PREDIV_A_Pos (16U)
12168#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
12169#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
12170#define RTC_PRER_PREDIV_S_Pos (0U)
12171#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
12172#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
12173
12174/******************** Bits definition for RTC_WUTR register *****************/
12175#define RTC_WUTR_WUT_Pos (0U)
12176#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
12177#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
12178
12179/******************** Bits definition for RTC_CALIBR register ***************/
12180#define RTC_CALIBR_DCS_Pos (7U)
12181#define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos)
12182#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
12183#define RTC_CALIBR_DC_Pos (0U)
12184#define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos)
12185#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
12186
12187/******************** Bits definition for RTC_ALRMAR register ***************/
12188#define RTC_ALRMAR_MSK4_Pos (31U)
12189#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
12190#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
12191#define RTC_ALRMAR_WDSEL_Pos (30U)
12192#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
12193#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
12194#define RTC_ALRMAR_DT_Pos (28U)
12195#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
12196#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
12197#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
12198#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
12199#define RTC_ALRMAR_DU_Pos (24U)
12200#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
12201#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
12202#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
12203#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
12204#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
12205#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
12206#define RTC_ALRMAR_MSK3_Pos (23U)
12207#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
12208#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
12209#define RTC_ALRMAR_PM_Pos (22U)
12210#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
12211#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
12212#define RTC_ALRMAR_HT_Pos (20U)
12213#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
12214#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
12215#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
12216#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
12217#define RTC_ALRMAR_HU_Pos (16U)
12218#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
12219#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
12220#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
12221#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
12222#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
12223#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
12224#define RTC_ALRMAR_MSK2_Pos (15U)
12225#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
12226#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
12227#define RTC_ALRMAR_MNT_Pos (12U)
12228#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
12229#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
12230#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
12231#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
12232#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
12233#define RTC_ALRMAR_MNU_Pos (8U)
12234#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
12235#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
12236#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
12237#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
12238#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
12239#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
12240#define RTC_ALRMAR_MSK1_Pos (7U)
12241#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
12242#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
12243#define RTC_ALRMAR_ST_Pos (4U)
12244#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
12245#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
12246#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
12247#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
12248#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
12249#define RTC_ALRMAR_SU_Pos (0U)
12250#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
12251#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
12252#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
12253#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
12254#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
12255#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
12256
12257/******************** Bits definition for RTC_ALRMBR register ***************/
12258#define RTC_ALRMBR_MSK4_Pos (31U)
12259#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
12260#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
12261#define RTC_ALRMBR_WDSEL_Pos (30U)
12262#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
12263#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
12264#define RTC_ALRMBR_DT_Pos (28U)
12265#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
12266#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
12267#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
12268#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
12269#define RTC_ALRMBR_DU_Pos (24U)
12270#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
12271#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
12272#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
12273#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
12274#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
12275#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
12276#define RTC_ALRMBR_MSK3_Pos (23U)
12277#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
12278#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
12279#define RTC_ALRMBR_PM_Pos (22U)
12280#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
12281#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
12282#define RTC_ALRMBR_HT_Pos (20U)
12283#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
12284#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
12285#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
12286#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
12287#define RTC_ALRMBR_HU_Pos (16U)
12288#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
12289#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
12290#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
12291#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
12292#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
12293#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
12294#define RTC_ALRMBR_MSK2_Pos (15U)
12295#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
12296#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
12297#define RTC_ALRMBR_MNT_Pos (12U)
12298#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
12299#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
12300#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
12301#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
12302#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
12303#define RTC_ALRMBR_MNU_Pos (8U)
12304#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
12305#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
12306#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
12307#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
12308#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
12309#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
12310#define RTC_ALRMBR_MSK1_Pos (7U)
12311#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
12312#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
12313#define RTC_ALRMBR_ST_Pos (4U)
12314#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
12315#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
12316#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
12317#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
12318#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
12319#define RTC_ALRMBR_SU_Pos (0U)
12320#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
12321#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
12322#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
12323#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
12324#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
12325#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
12326
12327/******************** Bits definition for RTC_WPR register ******************/
12328#define RTC_WPR_KEY_Pos (0U)
12329#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
12330#define RTC_WPR_KEY RTC_WPR_KEY_Msk
12331
12332/******************** Bits definition for RTC_SSR register ******************/
12333#define RTC_SSR_SS_Pos (0U)
12334#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
12335#define RTC_SSR_SS RTC_SSR_SS_Msk
12336
12337/******************** Bits definition for RTC_SHIFTR register ***************/
12338#define RTC_SHIFTR_SUBFS_Pos (0U)
12339#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
12340#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
12341#define RTC_SHIFTR_ADD1S_Pos (31U)
12342#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
12343#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
12344
12345/******************** Bits definition for RTC_TSTR register *****************/
12346#define RTC_TSTR_PM_Pos (22U)
12347#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
12348#define RTC_TSTR_PM RTC_TSTR_PM_Msk
12349#define RTC_TSTR_HT_Pos (20U)
12350#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
12351#define RTC_TSTR_HT RTC_TSTR_HT_Msk
12352#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
12353#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
12354#define RTC_TSTR_HU_Pos (16U)
12355#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
12356#define RTC_TSTR_HU RTC_TSTR_HU_Msk
12357#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
12358#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
12359#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
12360#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
12361#define RTC_TSTR_MNT_Pos (12U)
12362#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
12363#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
12364#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
12365#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
12366#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
12367#define RTC_TSTR_MNU_Pos (8U)
12368#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
12369#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
12370#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
12371#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
12372#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
12373#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
12374#define RTC_TSTR_ST_Pos (4U)
12375#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
12376#define RTC_TSTR_ST RTC_TSTR_ST_Msk
12377#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
12378#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
12379#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
12380#define RTC_TSTR_SU_Pos (0U)
12381#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
12382#define RTC_TSTR_SU RTC_TSTR_SU_Msk
12383#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
12384#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
12385#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
12386#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
12387
12388/******************** Bits definition for RTC_TSDR register *****************/
12389#define RTC_TSDR_WDU_Pos (13U)
12390#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
12391#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
12392#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
12393#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
12394#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
12395#define RTC_TSDR_MT_Pos (12U)
12396#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
12397#define RTC_TSDR_MT RTC_TSDR_MT_Msk
12398#define RTC_TSDR_MU_Pos (8U)
12399#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
12400#define RTC_TSDR_MU RTC_TSDR_MU_Msk
12401#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
12402#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
12403#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
12404#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
12405#define RTC_TSDR_DT_Pos (4U)
12406#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
12407#define RTC_TSDR_DT RTC_TSDR_DT_Msk
12408#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
12409#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
12410#define RTC_TSDR_DU_Pos (0U)
12411#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
12412#define RTC_TSDR_DU RTC_TSDR_DU_Msk
12413#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
12414#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
12415#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
12416#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
12417
12418/******************** Bits definition for RTC_TSSSR register ****************/
12419#define RTC_TSSSR_SS_Pos (0U)
12420#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
12421#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
12422
12423/******************** Bits definition for RTC_CAL register *****************/
12424#define RTC_CALR_CALP_Pos (15U)
12425#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
12426#define RTC_CALR_CALP RTC_CALR_CALP_Msk
12427#define RTC_CALR_CALW8_Pos (14U)
12428#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
12429#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
12430#define RTC_CALR_CALW16_Pos (13U)
12431#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
12432#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
12433#define RTC_CALR_CALM_Pos (0U)
12434#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
12435#define RTC_CALR_CALM RTC_CALR_CALM_Msk
12436#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
12437#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
12438#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
12439#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
12440#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
12441#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
12442#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
12443#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
12444#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
12445
12446/******************** Bits definition for RTC_TAFCR register ****************/
12447#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
12448#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)
12449#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
12450#define RTC_TAFCR_TSINSEL_Pos (17U)
12451#define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos)
12452#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
12453#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
12454#define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)
12455#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
12456#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
12457#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
12458#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
12459#define RTC_TAFCR_TAMPPRCH_Pos (13U)
12460#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
12461#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
12462#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
12463#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
12464#define RTC_TAFCR_TAMPFLT_Pos (11U)
12465#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
12466#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
12467#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
12468#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
12469#define RTC_TAFCR_TAMPFREQ_Pos (8U)
12470#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
12471#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
12472#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
12473#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
12474#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
12475#define RTC_TAFCR_TAMPTS_Pos (7U)
12476#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)
12477#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
12478#define RTC_TAFCR_TAMP2TRG_Pos (4U)
12479#define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)
12480#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
12481#define RTC_TAFCR_TAMP2E_Pos (3U)
12482#define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)
12483#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
12484#define RTC_TAFCR_TAMPIE_Pos (2U)
12485#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)
12486#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
12487#define RTC_TAFCR_TAMP1TRG_Pos (1U)
12488#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
12489#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
12490#define RTC_TAFCR_TAMP1E_Pos (0U)
12491#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)
12492#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
12493
12494/* Legacy defines */
12495#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
12496
12497/******************** Bits definition for RTC_ALRMASSR register *************/
12498#define RTC_ALRMASSR_MASKSS_Pos (24U)
12499#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
12500#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
12501#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
12502#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
12503#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
12504#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
12505#define RTC_ALRMASSR_SS_Pos (0U)
12506#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
12507#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
12508
12509/******************** Bits definition for RTC_ALRMBSSR register *************/
12510#define RTC_ALRMBSSR_MASKSS_Pos (24U)
12511#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
12512#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
12513#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
12514#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
12515#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
12516#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
12517#define RTC_ALRMBSSR_SS_Pos (0U)
12518#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
12519#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
12520
12521/******************** Bits definition for RTC_BKP0R register ****************/
12522#define RTC_BKP0R_Pos (0U)
12523#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
12524#define RTC_BKP0R RTC_BKP0R_Msk
12525
12526/******************** Bits definition for RTC_BKP1R register ****************/
12527#define RTC_BKP1R_Pos (0U)
12528#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
12529#define RTC_BKP1R RTC_BKP1R_Msk
12530
12531/******************** Bits definition for RTC_BKP2R register ****************/
12532#define RTC_BKP2R_Pos (0U)
12533#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
12534#define RTC_BKP2R RTC_BKP2R_Msk
12535
12536/******************** Bits definition for RTC_BKP3R register ****************/
12537#define RTC_BKP3R_Pos (0U)
12538#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
12539#define RTC_BKP3R RTC_BKP3R_Msk
12540
12541/******************** Bits definition for RTC_BKP4R register ****************/
12542#define RTC_BKP4R_Pos (0U)
12543#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
12544#define RTC_BKP4R RTC_BKP4R_Msk
12545
12546/******************** Bits definition for RTC_BKP5R register ****************/
12547#define RTC_BKP5R_Pos (0U)
12548#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
12549#define RTC_BKP5R RTC_BKP5R_Msk
12550
12551/******************** Bits definition for RTC_BKP6R register ****************/
12552#define RTC_BKP6R_Pos (0U)
12553#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
12554#define RTC_BKP6R RTC_BKP6R_Msk
12555
12556/******************** Bits definition for RTC_BKP7R register ****************/
12557#define RTC_BKP7R_Pos (0U)
12558#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
12559#define RTC_BKP7R RTC_BKP7R_Msk
12560
12561/******************** Bits definition for RTC_BKP8R register ****************/
12562#define RTC_BKP8R_Pos (0U)
12563#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
12564#define RTC_BKP8R RTC_BKP8R_Msk
12565
12566/******************** Bits definition for RTC_BKP9R register ****************/
12567#define RTC_BKP9R_Pos (0U)
12568#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
12569#define RTC_BKP9R RTC_BKP9R_Msk
12570
12571/******************** Bits definition for RTC_BKP10R register ***************/
12572#define RTC_BKP10R_Pos (0U)
12573#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
12574#define RTC_BKP10R RTC_BKP10R_Msk
12575
12576/******************** Bits definition for RTC_BKP11R register ***************/
12577#define RTC_BKP11R_Pos (0U)
12578#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
12579#define RTC_BKP11R RTC_BKP11R_Msk
12580
12581/******************** Bits definition for RTC_BKP12R register ***************/
12582#define RTC_BKP12R_Pos (0U)
12583#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
12584#define RTC_BKP12R RTC_BKP12R_Msk
12585
12586/******************** Bits definition for RTC_BKP13R register ***************/
12587#define RTC_BKP13R_Pos (0U)
12588#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
12589#define RTC_BKP13R RTC_BKP13R_Msk
12590
12591/******************** Bits definition for RTC_BKP14R register ***************/
12592#define RTC_BKP14R_Pos (0U)
12593#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
12594#define RTC_BKP14R RTC_BKP14R_Msk
12595
12596/******************** Bits definition for RTC_BKP15R register ***************/
12597#define RTC_BKP15R_Pos (0U)
12598#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
12599#define RTC_BKP15R RTC_BKP15R_Msk
12600
12601/******************** Bits definition for RTC_BKP16R register ***************/
12602#define RTC_BKP16R_Pos (0U)
12603#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
12604#define RTC_BKP16R RTC_BKP16R_Msk
12605
12606/******************** Bits definition for RTC_BKP17R register ***************/
12607#define RTC_BKP17R_Pos (0U)
12608#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
12609#define RTC_BKP17R RTC_BKP17R_Msk
12610
12611/******************** Bits definition for RTC_BKP18R register ***************/
12612#define RTC_BKP18R_Pos (0U)
12613#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
12614#define RTC_BKP18R RTC_BKP18R_Msk
12615
12616/******************** Bits definition for RTC_BKP19R register ***************/
12617#define RTC_BKP19R_Pos (0U)
12618#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
12619#define RTC_BKP19R RTC_BKP19R_Msk
12620
12621/******************** Number of backup registers ******************************/
12622#define RTC_BKP_NUMBER 0x000000014U
12623
12624/******************************************************************************/
12625/* */
12626/* Serial Audio Interface */
12627/* */
12628/******************************************************************************/
12629/******************** Bit definition for SAI_GCR register *******************/
12630#define SAI_GCR_SYNCIN_Pos (0U)
12631#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
12632#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
12633#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
12634#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
12635
12636#define SAI_GCR_SYNCOUT_Pos (4U)
12637#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
12638#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
12639#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
12640#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
12641
12642/******************* Bit definition for SAI_xCR1 register *******************/
12643#define SAI_xCR1_MODE_Pos (0U)
12644#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
12645#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
12646#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
12647#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
12648
12649#define SAI_xCR1_PRTCFG_Pos (2U)
12650#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
12651#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
12652#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
12653#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
12654
12655#define SAI_xCR1_DS_Pos (5U)
12656#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
12657#define SAI_xCR1_DS SAI_xCR1_DS_Msk
12658#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
12659#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
12660#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
12661
12662#define SAI_xCR1_LSBFIRST_Pos (8U)
12663#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
12664#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
12665#define SAI_xCR1_CKSTR_Pos (9U)
12666#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
12667#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
12668
12669#define SAI_xCR1_SYNCEN_Pos (10U)
12670#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
12671#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
12672#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
12673#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
12674
12675#define SAI_xCR1_MONO_Pos (12U)
12676#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
12677#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
12678#define SAI_xCR1_OUTDRIV_Pos (13U)
12679#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
12680#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
12681#define SAI_xCR1_SAIEN_Pos (16U)
12682#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
12683#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
12684#define SAI_xCR1_DMAEN_Pos (17U)
12685#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
12686#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
12687#define SAI_xCR1_NODIV_Pos (19U)
12688#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
12689#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
12690
12691#define SAI_xCR1_MCKDIV_Pos (20U)
12692#define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos)
12693#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
12694#define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos)
12695#define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos)
12696#define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos)
12697#define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos)
12698
12699/******************* Bit definition for SAI_xCR2 register *******************/
12700#define SAI_xCR2_FTH_Pos (0U)
12701#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
12702#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
12703#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
12704#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
12705#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
12706
12707#define SAI_xCR2_FFLUSH_Pos (3U)
12708#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
12709#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
12710#define SAI_xCR2_TRIS_Pos (4U)
12711#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
12712#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
12713#define SAI_xCR2_MUTE_Pos (5U)
12714#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
12715#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
12716#define SAI_xCR2_MUTEVAL_Pos (6U)
12717#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
12718#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
12719
12720#define SAI_xCR2_MUTECNT_Pos (7U)
12721#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
12722#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
12723#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
12724#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
12725#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
12726#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
12727#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
12728#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
12729
12730#define SAI_xCR2_CPL_Pos (13U)
12731#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
12732#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
12733
12734#define SAI_xCR2_COMP_Pos (14U)
12735#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
12736#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
12737#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
12738#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
12739
12740/****************** Bit definition for SAI_xFRCR register *******************/
12741#define SAI_xFRCR_FRL_Pos (0U)
12742#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
12743#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
12744#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
12745#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
12746#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
12747#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
12748#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
12749#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
12750#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
12751#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
12752
12753#define SAI_xFRCR_FSALL_Pos (8U)
12754#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
12755#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
12756#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
12757#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
12758#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
12759#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
12760#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
12761#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
12762#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
12763
12764#define SAI_xFRCR_FSDEF_Pos (16U)
12765#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
12766#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
12767#define SAI_xFRCR_FSPOL_Pos (17U)
12768#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
12769#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
12770#define SAI_xFRCR_FSOFF_Pos (18U)
12771#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
12772#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
12773/* Legacy defines */
12774#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
12775
12776/****************** Bit definition for SAI_xSLOTR register *******************/
12777#define SAI_xSLOTR_FBOFF_Pos (0U)
12778#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
12779#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
12780#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
12781#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
12782#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
12783#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
12784#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
12785
12786#define SAI_xSLOTR_SLOTSZ_Pos (6U)
12787#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
12788#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
12789#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
12790#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
12791
12792#define SAI_xSLOTR_NBSLOT_Pos (8U)
12793#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
12794#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
12795#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
12796#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
12797#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
12798#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
12799
12800#define SAI_xSLOTR_SLOTEN_Pos (16U)
12801#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
12802#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
12803
12804/******************* Bit definition for SAI_xIMR register *******************/
12805#define SAI_xIMR_OVRUDRIE_Pos (0U)
12806#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
12807#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
12808#define SAI_xIMR_MUTEDETIE_Pos (1U)
12809#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
12810#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
12811#define SAI_xIMR_WCKCFGIE_Pos (2U)
12812#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
12813#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
12814#define SAI_xIMR_FREQIE_Pos (3U)
12815#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
12816#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
12817#define SAI_xIMR_CNRDYIE_Pos (4U)
12818#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
12819#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
12820#define SAI_xIMR_AFSDETIE_Pos (5U)
12821#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
12822#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
12823#define SAI_xIMR_LFSDETIE_Pos (6U)
12824#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
12825#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
12826
12827/******************** Bit definition for SAI_xSR register *******************/
12828#define SAI_xSR_OVRUDR_Pos (0U)
12829#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
12830#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
12831#define SAI_xSR_MUTEDET_Pos (1U)
12832#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
12833#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
12834#define SAI_xSR_WCKCFG_Pos (2U)
12835#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
12836#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
12837#define SAI_xSR_FREQ_Pos (3U)
12838#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
12839#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
12840#define SAI_xSR_CNRDY_Pos (4U)
12841#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
12842#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
12843#define SAI_xSR_AFSDET_Pos (5U)
12844#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
12845#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
12846#define SAI_xSR_LFSDET_Pos (6U)
12847#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
12848#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
12849
12850#define SAI_xSR_FLVL_Pos (16U)
12851#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
12852#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
12853#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
12854#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
12855#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
12856
12857/****************** Bit definition for SAI_xCLRFR register ******************/
12858#define SAI_xCLRFR_COVRUDR_Pos (0U)
12859#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
12860#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
12861#define SAI_xCLRFR_CMUTEDET_Pos (1U)
12862#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
12863#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
12864#define SAI_xCLRFR_CWCKCFG_Pos (2U)
12865#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
12866#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
12867#define SAI_xCLRFR_CFREQ_Pos (3U)
12868#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
12869#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
12870#define SAI_xCLRFR_CCNRDY_Pos (4U)
12871#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
12872#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
12873#define SAI_xCLRFR_CAFSDET_Pos (5U)
12874#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
12875#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
12876#define SAI_xCLRFR_CLFSDET_Pos (6U)
12877#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
12878#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
12879
12880/****************** Bit definition for SAI_xDR register ******************/
12881#define SAI_xDR_DATA_Pos (0U)
12882#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
12883#define SAI_xDR_DATA SAI_xDR_DATA_Msk
12884
12885
12886/******************************************************************************/
12887/* */
12888/* SD host Interface */
12889/* */
12890/******************************************************************************/
12891/****************** Bit definition for SDIO_POWER register ******************/
12892#define SDIO_POWER_PWRCTRL_Pos (0U)
12893#define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos)
12894#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk
12895#define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos)
12896#define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos)
12897
12898/****************** Bit definition for SDIO_CLKCR register ******************/
12899#define SDIO_CLKCR_CLKDIV_Pos (0U)
12900#define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)
12901#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk
12902#define SDIO_CLKCR_CLKEN_Pos (8U)
12903#define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos)
12904#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk
12905#define SDIO_CLKCR_PWRSAV_Pos (9U)
12906#define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos)
12907#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk
12908#define SDIO_CLKCR_BYPASS_Pos (10U)
12909#define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos)
12910#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk
12911
12912#define SDIO_CLKCR_WIDBUS_Pos (11U)
12913#define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos)
12914#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk
12915#define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)
12916#define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)
12917
12918#define SDIO_CLKCR_NEGEDGE_Pos (13U)
12919#define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)
12920#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk
12921#define SDIO_CLKCR_HWFC_EN_Pos (14U)
12922#define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)
12923#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk
12924
12925/******************* Bit definition for SDIO_ARG register *******************/
12926#define SDIO_ARG_CMDARG_Pos (0U)
12927#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)
12928#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk
12929
12930/******************* Bit definition for SDIO_CMD register *******************/
12931#define SDIO_CMD_CMDINDEX_Pos (0U)
12932#define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos)
12933#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk
12934
12935#define SDIO_CMD_WAITRESP_Pos (6U)
12936#define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos)
12937#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk
12938#define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos)
12939#define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos)
12940
12941#define SDIO_CMD_WAITINT_Pos (8U)
12942#define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos)
12943#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk
12944#define SDIO_CMD_WAITPEND_Pos (9U)
12945#define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos)
12946#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk
12947#define SDIO_CMD_CPSMEN_Pos (10U)
12948#define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos)
12949#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk
12950#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
12951#define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)
12952#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk
12953#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
12954#define SDIO_CMD_ENCMDCOMPL_Msk (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)
12955#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk
12956#define SDIO_CMD_NIEN_Pos (13U)
12957#define SDIO_CMD_NIEN_Msk (0x1UL << SDIO_CMD_NIEN_Pos)
12958#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk
12959#define SDIO_CMD_CEATACMD_Pos (14U)
12960#define SDIO_CMD_CEATACMD_Msk (0x1UL << SDIO_CMD_CEATACMD_Pos)
12961#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk
12962
12963/***************** Bit definition for SDIO_RESPCMD register *****************/
12964#define SDIO_RESPCMD_RESPCMD_Pos (0U)
12965#define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)
12966#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk
12967
12968/****************** Bit definition for SDIO_RESP0 register ******************/
12969#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
12970#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)
12971#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk
12972
12973/****************** Bit definition for SDIO_RESP1 register ******************/
12974#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
12975#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)
12976#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk
12977
12978/****************** Bit definition for SDIO_RESP2 register ******************/
12979#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
12980#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)
12981#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk
12982
12983/****************** Bit definition for SDIO_RESP3 register ******************/
12984#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
12985#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)
12986#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk
12987
12988/****************** Bit definition for SDIO_RESP4 register ******************/
12989#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
12990#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)
12991#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk
12992
12993/****************** Bit definition for SDIO_DTIMER register *****************/
12994#define SDIO_DTIMER_DATATIME_Pos (0U)
12995#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)
12996#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk
12997
12998/****************** Bit definition for SDIO_DLEN register *******************/
12999#define SDIO_DLEN_DATALENGTH_Pos (0U)
13000#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)
13001#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk
13002
13003/****************** Bit definition for SDIO_DCTRL register ******************/
13004#define SDIO_DCTRL_DTEN_Pos (0U)
13005#define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos)
13006#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk
13007#define SDIO_DCTRL_DTDIR_Pos (1U)
13008#define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos)
13009#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk
13010#define SDIO_DCTRL_DTMODE_Pos (2U)
13011#define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos)
13012#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk
13013#define SDIO_DCTRL_DMAEN_Pos (3U)
13014#define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos)
13015#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk
13016
13017#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
13018#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)
13019#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk
13020#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
13021#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
13022#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
13023#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
13024
13025#define SDIO_DCTRL_RWSTART_Pos (8U)
13026#define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos)
13027#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk
13028#define SDIO_DCTRL_RWSTOP_Pos (9U)
13029#define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos)
13030#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk
13031#define SDIO_DCTRL_RWMOD_Pos (10U)
13032#define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos)
13033#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk
13034#define SDIO_DCTRL_SDIOEN_Pos (11U)
13035#define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos)
13036#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk
13037
13038/****************** Bit definition for SDIO_DCOUNT register *****************/
13039#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
13040#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)
13041#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk
13042
13043/****************** Bit definition for SDIO_STA register ********************/
13044#define SDIO_STA_CCRCFAIL_Pos (0U)
13045#define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos)
13046#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk
13047#define SDIO_STA_DCRCFAIL_Pos (1U)
13048#define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos)
13049#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk
13050#define SDIO_STA_CTIMEOUT_Pos (2U)
13051#define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos)
13052#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk
13053#define SDIO_STA_DTIMEOUT_Pos (3U)
13054#define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos)
13055#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk
13056#define SDIO_STA_TXUNDERR_Pos (4U)
13057#define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos)
13058#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk
13059#define SDIO_STA_RXOVERR_Pos (5U)
13060#define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos)
13061#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk
13062#define SDIO_STA_CMDREND_Pos (6U)
13063#define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos)
13064#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk
13065#define SDIO_STA_CMDSENT_Pos (7U)
13066#define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos)
13067#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk
13068#define SDIO_STA_DATAEND_Pos (8U)
13069#define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos)
13070#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk
13071#define SDIO_STA_STBITERR_Pos (9U)
13072#define SDIO_STA_STBITERR_Msk (0x1UL << SDIO_STA_STBITERR_Pos)
13073#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk
13074#define SDIO_STA_DBCKEND_Pos (10U)
13075#define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos)
13076#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk
13077#define SDIO_STA_CMDACT_Pos (11U)
13078#define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos)
13079#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk
13080#define SDIO_STA_TXACT_Pos (12U)
13081#define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos)
13082#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk
13083#define SDIO_STA_RXACT_Pos (13U)
13084#define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos)
13085#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk
13086#define SDIO_STA_TXFIFOHE_Pos (14U)
13087#define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos)
13088#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk
13089#define SDIO_STA_RXFIFOHF_Pos (15U)
13090#define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos)
13091#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk
13092#define SDIO_STA_TXFIFOF_Pos (16U)
13093#define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos)
13094#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk
13095#define SDIO_STA_RXFIFOF_Pos (17U)
13096#define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos)
13097#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk
13098#define SDIO_STA_TXFIFOE_Pos (18U)
13099#define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos)
13100#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk
13101#define SDIO_STA_RXFIFOE_Pos (19U)
13102#define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos)
13103#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk
13104#define SDIO_STA_TXDAVL_Pos (20U)
13105#define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos)
13106#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk
13107#define SDIO_STA_RXDAVL_Pos (21U)
13108#define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos)
13109#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk
13110#define SDIO_STA_SDIOIT_Pos (22U)
13111#define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos)
13112#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk
13113#define SDIO_STA_CEATAEND_Pos (23U)
13114#define SDIO_STA_CEATAEND_Msk (0x1UL << SDIO_STA_CEATAEND_Pos)
13115#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk
13116
13117/******************* Bit definition for SDIO_ICR register *******************/
13118#define SDIO_ICR_CCRCFAILC_Pos (0U)
13119#define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos)
13120#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk
13121#define SDIO_ICR_DCRCFAILC_Pos (1U)
13122#define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos)
13123#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk
13124#define SDIO_ICR_CTIMEOUTC_Pos (2U)
13125#define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)
13126#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk
13127#define SDIO_ICR_DTIMEOUTC_Pos (3U)
13128#define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)
13129#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk
13130#define SDIO_ICR_TXUNDERRC_Pos (4U)
13131#define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos)
13132#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk
13133#define SDIO_ICR_RXOVERRC_Pos (5U)
13134#define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos)
13135#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk
13136#define SDIO_ICR_CMDRENDC_Pos (6U)
13137#define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos)
13138#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk
13139#define SDIO_ICR_CMDSENTC_Pos (7U)
13140#define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos)
13141#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk
13142#define SDIO_ICR_DATAENDC_Pos (8U)
13143#define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos)
13144#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk
13145#define SDIO_ICR_STBITERRC_Pos (9U)
13146#define SDIO_ICR_STBITERRC_Msk (0x1UL << SDIO_ICR_STBITERRC_Pos)
13147#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk
13148#define SDIO_ICR_DBCKENDC_Pos (10U)
13149#define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos)
13150#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk
13151#define SDIO_ICR_SDIOITC_Pos (22U)
13152#define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos)
13153#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk
13154#define SDIO_ICR_CEATAENDC_Pos (23U)
13155#define SDIO_ICR_CEATAENDC_Msk (0x1UL << SDIO_ICR_CEATAENDC_Pos)
13156#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk
13157
13158/****************** Bit definition for SDIO_MASK register *******************/
13159#define SDIO_MASK_CCRCFAILIE_Pos (0U)
13160#define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)
13161#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk
13162#define SDIO_MASK_DCRCFAILIE_Pos (1U)
13163#define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)
13164#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk
13165#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
13166#define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)
13167#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk
13168#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
13169#define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)
13170#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk
13171#define SDIO_MASK_TXUNDERRIE_Pos (4U)
13172#define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)
13173#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk
13174#define SDIO_MASK_RXOVERRIE_Pos (5U)
13175#define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos)
13176#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk
13177#define SDIO_MASK_CMDRENDIE_Pos (6U)
13178#define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos)
13179#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk
13180#define SDIO_MASK_CMDSENTIE_Pos (7U)
13181#define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos)
13182#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk
13183#define SDIO_MASK_DATAENDIE_Pos (8U)
13184#define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos)
13185#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk
13186#define SDIO_MASK_STBITERRIE_Pos (9U)
13187#define SDIO_MASK_STBITERRIE_Msk (0x1UL << SDIO_MASK_STBITERRIE_Pos)
13188#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk
13189#define SDIO_MASK_DBCKENDIE_Pos (10U)
13190#define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos)
13191#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk
13192#define SDIO_MASK_CMDACTIE_Pos (11U)
13193#define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos)
13194#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk
13195#define SDIO_MASK_TXACTIE_Pos (12U)
13196#define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos)
13197#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk
13198#define SDIO_MASK_RXACTIE_Pos (13U)
13199#define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos)
13200#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk
13201#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
13202#define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)
13203#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk
13204#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
13205#define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)
13206#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk
13207#define SDIO_MASK_TXFIFOFIE_Pos (16U)
13208#define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)
13209#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk
13210#define SDIO_MASK_RXFIFOFIE_Pos (17U)
13211#define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)
13212#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk
13213#define SDIO_MASK_TXFIFOEIE_Pos (18U)
13214#define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)
13215#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk
13216#define SDIO_MASK_RXFIFOEIE_Pos (19U)
13217#define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)
13218#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk
13219#define SDIO_MASK_TXDAVLIE_Pos (20U)
13220#define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos)
13221#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk
13222#define SDIO_MASK_RXDAVLIE_Pos (21U)
13223#define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos)
13224#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk
13225#define SDIO_MASK_SDIOITIE_Pos (22U)
13226#define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos)
13227#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk
13228#define SDIO_MASK_CEATAENDIE_Pos (23U)
13229#define SDIO_MASK_CEATAENDIE_Msk (0x1UL << SDIO_MASK_CEATAENDIE_Pos)
13230#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk
13231
13232/***************** Bit definition for SDIO_FIFOCNT register *****************/
13233#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
13234#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)
13235#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk
13236
13237/****************** Bit definition for SDIO_FIFO register *******************/
13238#define SDIO_FIFO_FIFODATA_Pos (0U)
13239#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)
13240#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk
13241
13242/******************************************************************************/
13243/* */
13244/* Serial Peripheral Interface */
13245/* */
13246/******************************************************************************/
13247#define SPI_I2S_FULLDUPLEX_SUPPORT
13248
13249/******************* Bit definition for SPI_CR1 register ********************/
13250#define SPI_CR1_CPHA_Pos (0U)
13251#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
13252#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
13253#define SPI_CR1_CPOL_Pos (1U)
13254#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
13255#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
13256#define SPI_CR1_MSTR_Pos (2U)
13257#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
13258#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
13259
13260#define SPI_CR1_BR_Pos (3U)
13261#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
13262#define SPI_CR1_BR SPI_CR1_BR_Msk
13263#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
13264#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
13265#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
13266
13267#define SPI_CR1_SPE_Pos (6U)
13268#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
13269#define SPI_CR1_SPE SPI_CR1_SPE_Msk
13270#define SPI_CR1_LSBFIRST_Pos (7U)
13271#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
13272#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
13273#define SPI_CR1_SSI_Pos (8U)
13274#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
13275#define SPI_CR1_SSI SPI_CR1_SSI_Msk
13276#define SPI_CR1_SSM_Pos (9U)
13277#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
13278#define SPI_CR1_SSM SPI_CR1_SSM_Msk
13279#define SPI_CR1_RXONLY_Pos (10U)
13280#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
13281#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
13282#define SPI_CR1_DFF_Pos (11U)
13283#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)
13284#define SPI_CR1_DFF SPI_CR1_DFF_Msk
13285#define SPI_CR1_CRCNEXT_Pos (12U)
13286#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
13287#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
13288#define SPI_CR1_CRCEN_Pos (13U)
13289#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
13290#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
13291#define SPI_CR1_BIDIOE_Pos (14U)
13292#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
13293#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
13294#define SPI_CR1_BIDIMODE_Pos (15U)
13295#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
13296#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
13297
13298/******************* Bit definition for SPI_CR2 register ********************/
13299#define SPI_CR2_RXDMAEN_Pos (0U)
13300#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
13301#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
13302#define SPI_CR2_TXDMAEN_Pos (1U)
13303#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
13304#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
13305#define SPI_CR2_SSOE_Pos (2U)
13306#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
13307#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
13308#define SPI_CR2_FRF_Pos (4U)
13309#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
13310#define SPI_CR2_FRF SPI_CR2_FRF_Msk
13311#define SPI_CR2_ERRIE_Pos (5U)
13312#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
13313#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
13314#define SPI_CR2_RXNEIE_Pos (6U)
13315#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
13316#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
13317#define SPI_CR2_TXEIE_Pos (7U)
13318#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
13319#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
13320
13321/******************** Bit definition for SPI_SR register ********************/
13322#define SPI_SR_RXNE_Pos (0U)
13323#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
13324#define SPI_SR_RXNE SPI_SR_RXNE_Msk
13325#define SPI_SR_TXE_Pos (1U)
13326#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
13327#define SPI_SR_TXE SPI_SR_TXE_Msk
13328#define SPI_SR_CHSIDE_Pos (2U)
13329#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
13330#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
13331#define SPI_SR_UDR_Pos (3U)
13332#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
13333#define SPI_SR_UDR SPI_SR_UDR_Msk
13334#define SPI_SR_CRCERR_Pos (4U)
13335#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
13336#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
13337#define SPI_SR_MODF_Pos (5U)
13338#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
13339#define SPI_SR_MODF SPI_SR_MODF_Msk
13340#define SPI_SR_OVR_Pos (6U)
13341#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
13342#define SPI_SR_OVR SPI_SR_OVR_Msk
13343#define SPI_SR_BSY_Pos (7U)
13344#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
13345#define SPI_SR_BSY SPI_SR_BSY_Msk
13346#define SPI_SR_FRE_Pos (8U)
13347#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
13348#define SPI_SR_FRE SPI_SR_FRE_Msk
13349
13350/******************** Bit definition for SPI_DR register ********************/
13351#define SPI_DR_DR_Pos (0U)
13352#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
13353#define SPI_DR_DR SPI_DR_DR_Msk
13354
13355/******************* Bit definition for SPI_CRCPR register ******************/
13356#define SPI_CRCPR_CRCPOLY_Pos (0U)
13357#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
13358#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
13359
13360/****************** Bit definition for SPI_RXCRCR register ******************/
13361#define SPI_RXCRCR_RXCRC_Pos (0U)
13362#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
13363#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
13364
13365/****************** Bit definition for SPI_TXCRCR register ******************/
13366#define SPI_TXCRCR_TXCRC_Pos (0U)
13367#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
13368#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
13369
13370/****************** Bit definition for SPI_I2SCFGR register *****************/
13371#define SPI_I2SCFGR_CHLEN_Pos (0U)
13372#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
13373#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
13374
13375#define SPI_I2SCFGR_DATLEN_Pos (1U)
13376#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
13377#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
13378#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
13379#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
13380
13381#define SPI_I2SCFGR_CKPOL_Pos (3U)
13382#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
13383#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
13384
13385#define SPI_I2SCFGR_I2SSTD_Pos (4U)
13386#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
13387#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
13388#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
13389#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
13390
13391#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
13392#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
13393#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
13394
13395#define SPI_I2SCFGR_I2SCFG_Pos (8U)
13396#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
13397#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
13398#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
13399#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
13400
13401#define SPI_I2SCFGR_I2SE_Pos (10U)
13402#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
13403#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
13404#define SPI_I2SCFGR_I2SMOD_Pos (11U)
13405#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
13406#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
13407
13408/****************** Bit definition for SPI_I2SPR register *******************/
13409#define SPI_I2SPR_I2SDIV_Pos (0U)
13410#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
13411#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
13412#define SPI_I2SPR_ODD_Pos (8U)
13413#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
13414#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
13415#define SPI_I2SPR_MCKOE_Pos (9U)
13416#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
13417#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
13418
13419/******************************************************************************/
13420/* */
13421/* SYSCFG */
13422/* */
13423/******************************************************************************/
13424/****************** Bit definition for SYSCFG_MEMRMP register ***************/
13425#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
13426#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
13427#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
13428#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
13429#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
13430#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
13431#define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
13432#define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_UFB_MODE_Pos)
13433#define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk
13434#define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
13435#define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
13436#define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk
13437#define SYSCFG_MEMRMP_SWP_FMC_0 (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
13438/* Legacy Defines */
13439#define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
13440/****************** Bit definition for SYSCFG_PMC register ******************/
13441#define SYSCFG_PMC_ADCxDC2_Pos (16U)
13442#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos)
13443#define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk
13444#define SYSCFG_PMC_ADC1DC2_Pos (16U)
13445#define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)
13446#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk
13447#define SYSCFG_PMC_ADC2DC2_Pos (17U)
13448#define SYSCFG_PMC_ADC2DC2_Msk (0x1UL << SYSCFG_PMC_ADC2DC2_Pos)
13449#define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk
13450#define SYSCFG_PMC_ADC3DC2_Pos (18U)
13451#define SYSCFG_PMC_ADC3DC2_Msk (0x1UL << SYSCFG_PMC_ADC3DC2_Pos)
13452#define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk
13453#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
13454#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)
13455#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk
13456/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
13457#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
13458
13459/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
13460#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
13461#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
13462#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
13463#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
13464#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
13465#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
13466#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
13467#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
13468#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
13469#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
13470#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
13471#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
13475#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
13476#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
13477#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
13478#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
13479#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
13480#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
13481#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
13482#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
13483#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
13484#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
13485#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
13486
13490#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
13491#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
13492#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
13493#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
13494#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
13495#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
13496#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
13497#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
13498#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
13499#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
13500#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
13501
13505#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
13506#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
13507#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
13508#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
13509#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
13510#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
13511#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
13512#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
13513#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
13514#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
13515#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
13516
13520#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
13521#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
13522#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
13523#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
13524#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
13525#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
13526#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
13527#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
13528#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
13529#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
13530#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
13531
13532/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
13533#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
13534#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
13535#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
13536#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
13537#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
13538#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
13539#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
13540#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
13541#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
13542#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
13543#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
13544#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
13545
13549#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
13550#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
13551#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
13552#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
13553#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
13554#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
13555#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
13556#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
13557#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
13558#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
13559#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
13560
13564#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
13565#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
13566#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
13567#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
13568#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
13569#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
13570#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
13571#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
13572#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
13573#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
13574#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
13575
13579#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
13580#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
13581#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
13582#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
13583#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
13584#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
13585#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
13586#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
13587#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
13588#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
13589#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
13590
13594#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
13595#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
13596#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
13597#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
13598#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
13599#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
13600#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
13601#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
13602#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
13603#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
13604#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
13605
13606/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
13607#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
13608#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
13609#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
13610#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
13611#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
13612#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
13613#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
13614#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
13615#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
13616#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
13617#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
13618#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
13619
13623#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
13624#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
13625#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
13626#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
13627#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
13628#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
13629#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
13630#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
13631#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
13632#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
13633
13637#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
13638#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
13639#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
13640#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
13641#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
13642#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
13643#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
13644#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
13645#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
13646#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
13647
13651#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
13652#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
13653#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
13654#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
13655#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
13656#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
13657#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
13658#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
13659#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
13660#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
13661
13665#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
13666#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
13667#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
13668#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
13669#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
13670#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
13671#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
13672#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
13673#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
13674#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
13675
13676
13677/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
13678#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
13679#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
13680#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
13681#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
13682#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
13683#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
13684#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
13685#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
13686#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
13687#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
13688#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
13689#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
13690
13694#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
13695#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
13696#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
13697#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
13698#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
13699#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
13700#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
13701#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
13702#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
13703#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
13704
13708#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
13709#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
13710#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
13711#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
13712#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
13713#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
13714#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
13715#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
13716#define SYSCFG_EXTICR4_EXTI13_PI 0x0008U
13717#define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U
13718
13722#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
13723#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
13724#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
13725#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
13726#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
13727#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
13728#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
13729#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
13730#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
13731#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
13732
13736#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
13737#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
13738#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
13739#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
13740#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
13741#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
13742#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
13743#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
13744#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
13745#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
13746
13747/****************** Bit definition for SYSCFG_CMPCR register ****************/
13748#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
13749#define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
13750#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk
13751#define SYSCFG_CMPCR_READY_Pos (8U)
13752#define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)
13753#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk
13754
13755/******************************************************************************/
13756/* */
13757/* TIM */
13758/* */
13759/******************************************************************************/
13760/******************* Bit definition for TIM_CR1 register ********************/
13761#define TIM_CR1_CEN_Pos (0U)
13762#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
13763#define TIM_CR1_CEN TIM_CR1_CEN_Msk
13764#define TIM_CR1_UDIS_Pos (1U)
13765#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
13766#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
13767#define TIM_CR1_URS_Pos (2U)
13768#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
13769#define TIM_CR1_URS TIM_CR1_URS_Msk
13770#define TIM_CR1_OPM_Pos (3U)
13771#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
13772#define TIM_CR1_OPM TIM_CR1_OPM_Msk
13773#define TIM_CR1_DIR_Pos (4U)
13774#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
13775#define TIM_CR1_DIR TIM_CR1_DIR_Msk
13776
13777#define TIM_CR1_CMS_Pos (5U)
13778#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
13779#define TIM_CR1_CMS TIM_CR1_CMS_Msk
13780#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
13781#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
13782
13783#define TIM_CR1_ARPE_Pos (7U)
13784#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
13785#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
13786
13787#define TIM_CR1_CKD_Pos (8U)
13788#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
13789#define TIM_CR1_CKD TIM_CR1_CKD_Msk
13790#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
13791#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
13792
13793/******************* Bit definition for TIM_CR2 register ********************/
13794#define TIM_CR2_CCPC_Pos (0U)
13795#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
13796#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
13797#define TIM_CR2_CCUS_Pos (2U)
13798#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
13799#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
13800#define TIM_CR2_CCDS_Pos (3U)
13801#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
13802#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
13803
13804#define TIM_CR2_MMS_Pos (4U)
13805#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
13806#define TIM_CR2_MMS TIM_CR2_MMS_Msk
13807#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
13808#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
13809#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
13810
13811#define TIM_CR2_TI1S_Pos (7U)
13812#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
13813#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
13814#define TIM_CR2_OIS1_Pos (8U)
13815#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
13816#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
13817#define TIM_CR2_OIS1N_Pos (9U)
13818#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
13819#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
13820#define TIM_CR2_OIS2_Pos (10U)
13821#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
13822#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
13823#define TIM_CR2_OIS2N_Pos (11U)
13824#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
13825#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
13826#define TIM_CR2_OIS3_Pos (12U)
13827#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
13828#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
13829#define TIM_CR2_OIS3N_Pos (13U)
13830#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
13831#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
13832#define TIM_CR2_OIS4_Pos (14U)
13833#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
13834#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
13835
13836/******************* Bit definition for TIM_SMCR register *******************/
13837#define TIM_SMCR_SMS_Pos (0U)
13838#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
13839#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
13840#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
13841#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
13842#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
13843
13844#define TIM_SMCR_TS_Pos (4U)
13845#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
13846#define TIM_SMCR_TS TIM_SMCR_TS_Msk
13847#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
13848#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
13849#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
13850
13851#define TIM_SMCR_MSM_Pos (7U)
13852#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
13853#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
13854
13855#define TIM_SMCR_ETF_Pos (8U)
13856#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
13857#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
13858#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
13859#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
13860#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
13861#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
13862
13863#define TIM_SMCR_ETPS_Pos (12U)
13864#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
13865#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
13866#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
13867#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
13868
13869#define TIM_SMCR_ECE_Pos (14U)
13870#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
13871#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
13872#define TIM_SMCR_ETP_Pos (15U)
13873#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
13874#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
13875
13876/******************* Bit definition for TIM_DIER register *******************/
13877#define TIM_DIER_UIE_Pos (0U)
13878#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
13879#define TIM_DIER_UIE TIM_DIER_UIE_Msk
13880#define TIM_DIER_CC1IE_Pos (1U)
13881#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
13882#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
13883#define TIM_DIER_CC2IE_Pos (2U)
13884#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
13885#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
13886#define TIM_DIER_CC3IE_Pos (3U)
13887#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
13888#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
13889#define TIM_DIER_CC4IE_Pos (4U)
13890#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
13891#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
13892#define TIM_DIER_COMIE_Pos (5U)
13893#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
13894#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
13895#define TIM_DIER_TIE_Pos (6U)
13896#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
13897#define TIM_DIER_TIE TIM_DIER_TIE_Msk
13898#define TIM_DIER_BIE_Pos (7U)
13899#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
13900#define TIM_DIER_BIE TIM_DIER_BIE_Msk
13901#define TIM_DIER_UDE_Pos (8U)
13902#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
13903#define TIM_DIER_UDE TIM_DIER_UDE_Msk
13904#define TIM_DIER_CC1DE_Pos (9U)
13905#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
13906#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
13907#define TIM_DIER_CC2DE_Pos (10U)
13908#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
13909#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
13910#define TIM_DIER_CC3DE_Pos (11U)
13911#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
13912#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
13913#define TIM_DIER_CC4DE_Pos (12U)
13914#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
13915#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
13916#define TIM_DIER_COMDE_Pos (13U)
13917#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
13918#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
13919#define TIM_DIER_TDE_Pos (14U)
13920#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
13921#define TIM_DIER_TDE TIM_DIER_TDE_Msk
13922
13923/******************** Bit definition for TIM_SR register ********************/
13924#define TIM_SR_UIF_Pos (0U)
13925#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
13926#define TIM_SR_UIF TIM_SR_UIF_Msk
13927#define TIM_SR_CC1IF_Pos (1U)
13928#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
13929#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
13930#define TIM_SR_CC2IF_Pos (2U)
13931#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
13932#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
13933#define TIM_SR_CC3IF_Pos (3U)
13934#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
13935#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
13936#define TIM_SR_CC4IF_Pos (4U)
13937#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
13938#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
13939#define TIM_SR_COMIF_Pos (5U)
13940#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
13941#define TIM_SR_COMIF TIM_SR_COMIF_Msk
13942#define TIM_SR_TIF_Pos (6U)
13943#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
13944#define TIM_SR_TIF TIM_SR_TIF_Msk
13945#define TIM_SR_BIF_Pos (7U)
13946#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
13947#define TIM_SR_BIF TIM_SR_BIF_Msk
13948#define TIM_SR_CC1OF_Pos (9U)
13949#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
13950#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
13951#define TIM_SR_CC2OF_Pos (10U)
13952#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
13953#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
13954#define TIM_SR_CC3OF_Pos (11U)
13955#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
13956#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
13957#define TIM_SR_CC4OF_Pos (12U)
13958#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
13959#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
13960
13961/******************* Bit definition for TIM_EGR register ********************/
13962#define TIM_EGR_UG_Pos (0U)
13963#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
13964#define TIM_EGR_UG TIM_EGR_UG_Msk
13965#define TIM_EGR_CC1G_Pos (1U)
13966#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
13967#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
13968#define TIM_EGR_CC2G_Pos (2U)
13969#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
13970#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
13971#define TIM_EGR_CC3G_Pos (3U)
13972#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
13973#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
13974#define TIM_EGR_CC4G_Pos (4U)
13975#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
13976#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
13977#define TIM_EGR_COMG_Pos (5U)
13978#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
13979#define TIM_EGR_COMG TIM_EGR_COMG_Msk
13980#define TIM_EGR_TG_Pos (6U)
13981#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
13982#define TIM_EGR_TG TIM_EGR_TG_Msk
13983#define TIM_EGR_BG_Pos (7U)
13984#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
13985#define TIM_EGR_BG TIM_EGR_BG_Msk
13986
13987/****************** Bit definition for TIM_CCMR1 register *******************/
13988#define TIM_CCMR1_CC1S_Pos (0U)
13989#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
13990#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
13991#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
13992#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
13993
13994#define TIM_CCMR1_OC1FE_Pos (2U)
13995#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
13996#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
13997#define TIM_CCMR1_OC1PE_Pos (3U)
13998#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
13999#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
14000
14001#define TIM_CCMR1_OC1M_Pos (4U)
14002#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
14003#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
14004#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
14005#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
14006#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
14007
14008#define TIM_CCMR1_OC1CE_Pos (7U)
14009#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
14010#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
14011
14012#define TIM_CCMR1_CC2S_Pos (8U)
14013#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
14014#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
14015#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
14016#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
14017
14018#define TIM_CCMR1_OC2FE_Pos (10U)
14019#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
14020#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
14021#define TIM_CCMR1_OC2PE_Pos (11U)
14022#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
14023#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
14024
14025#define TIM_CCMR1_OC2M_Pos (12U)
14026#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
14027#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
14028#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
14029#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
14030#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
14031
14032#define TIM_CCMR1_OC2CE_Pos (15U)
14033#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
14034#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
14035
14036/*----------------------------------------------------------------------------*/
14037
14038#define TIM_CCMR1_IC1PSC_Pos (2U)
14039#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
14040#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
14041#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
14042#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
14043
14044#define TIM_CCMR1_IC1F_Pos (4U)
14045#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
14046#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
14047#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
14048#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
14049#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
14050#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
14051
14052#define TIM_CCMR1_IC2PSC_Pos (10U)
14053#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
14054#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
14055#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
14056#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
14057
14058#define TIM_CCMR1_IC2F_Pos (12U)
14059#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
14060#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
14061#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
14062#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
14063#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
14064#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
14065
14066/****************** Bit definition for TIM_CCMR2 register *******************/
14067#define TIM_CCMR2_CC3S_Pos (0U)
14068#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
14069#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
14070#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
14071#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
14072
14073#define TIM_CCMR2_OC3FE_Pos (2U)
14074#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
14075#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
14076#define TIM_CCMR2_OC3PE_Pos (3U)
14077#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
14078#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
14079
14080#define TIM_CCMR2_OC3M_Pos (4U)
14081#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
14082#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
14083#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
14084#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
14085#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
14086
14087#define TIM_CCMR2_OC3CE_Pos (7U)
14088#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
14089#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
14090
14091#define TIM_CCMR2_CC4S_Pos (8U)
14092#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
14093#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
14094#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
14095#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
14096
14097#define TIM_CCMR2_OC4FE_Pos (10U)
14098#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
14099#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
14100#define TIM_CCMR2_OC4PE_Pos (11U)
14101#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
14102#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
14103
14104#define TIM_CCMR2_OC4M_Pos (12U)
14105#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
14106#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
14107#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
14108#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
14109#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
14110
14111#define TIM_CCMR2_OC4CE_Pos (15U)
14112#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
14113#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
14114
14115/*----------------------------------------------------------------------------*/
14116
14117#define TIM_CCMR2_IC3PSC_Pos (2U)
14118#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
14119#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
14120#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
14121#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
14122
14123#define TIM_CCMR2_IC3F_Pos (4U)
14124#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
14125#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
14126#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
14127#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
14128#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
14129#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
14130
14131#define TIM_CCMR2_IC4PSC_Pos (10U)
14132#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
14133#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
14134#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
14135#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
14136
14137#define TIM_CCMR2_IC4F_Pos (12U)
14138#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
14139#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
14140#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
14141#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
14142#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
14143#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
14144
14145/******************* Bit definition for TIM_CCER register *******************/
14146#define TIM_CCER_CC1E_Pos (0U)
14147#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
14148#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
14149#define TIM_CCER_CC1P_Pos (1U)
14150#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
14151#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
14152#define TIM_CCER_CC1NE_Pos (2U)
14153#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
14154#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
14155#define TIM_CCER_CC1NP_Pos (3U)
14156#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
14157#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
14158#define TIM_CCER_CC2E_Pos (4U)
14159#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
14160#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
14161#define TIM_CCER_CC2P_Pos (5U)
14162#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
14163#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
14164#define TIM_CCER_CC2NE_Pos (6U)
14165#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
14166#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
14167#define TIM_CCER_CC2NP_Pos (7U)
14168#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
14169#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
14170#define TIM_CCER_CC3E_Pos (8U)
14171#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
14172#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
14173#define TIM_CCER_CC3P_Pos (9U)
14174#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
14175#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
14176#define TIM_CCER_CC3NE_Pos (10U)
14177#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
14178#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
14179#define TIM_CCER_CC3NP_Pos (11U)
14180#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
14181#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
14182#define TIM_CCER_CC4E_Pos (12U)
14183#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
14184#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
14185#define TIM_CCER_CC4P_Pos (13U)
14186#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
14187#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
14188#define TIM_CCER_CC4NP_Pos (15U)
14189#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
14190#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
14191
14192/******************* Bit definition for TIM_CNT register ********************/
14193#define TIM_CNT_CNT_Pos (0U)
14194#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
14195#define TIM_CNT_CNT TIM_CNT_CNT_Msk
14196
14197/******************* Bit definition for TIM_PSC register ********************/
14198#define TIM_PSC_PSC_Pos (0U)
14199#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
14200#define TIM_PSC_PSC TIM_PSC_PSC_Msk
14201
14202/******************* Bit definition for TIM_ARR register ********************/
14203#define TIM_ARR_ARR_Pos (0U)
14204#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
14205#define TIM_ARR_ARR TIM_ARR_ARR_Msk
14206
14207/******************* Bit definition for TIM_RCR register ********************/
14208#define TIM_RCR_REP_Pos (0U)
14209#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
14210#define TIM_RCR_REP TIM_RCR_REP_Msk
14211
14212/******************* Bit definition for TIM_CCR1 register *******************/
14213#define TIM_CCR1_CCR1_Pos (0U)
14214#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
14215#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
14216
14217/******************* Bit definition for TIM_CCR2 register *******************/
14218#define TIM_CCR2_CCR2_Pos (0U)
14219#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
14220#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
14221
14222/******************* Bit definition for TIM_CCR3 register *******************/
14223#define TIM_CCR3_CCR3_Pos (0U)
14224#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
14225#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
14226
14227/******************* Bit definition for TIM_CCR4 register *******************/
14228#define TIM_CCR4_CCR4_Pos (0U)
14229#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
14230#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
14231
14232/******************* Bit definition for TIM_BDTR register *******************/
14233#define TIM_BDTR_DTG_Pos (0U)
14234#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
14235#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
14236#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
14237#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
14238#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
14239#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
14240#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
14241#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
14242#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
14243#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
14244
14245#define TIM_BDTR_LOCK_Pos (8U)
14246#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
14247#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
14248#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
14249#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
14250
14251#define TIM_BDTR_OSSI_Pos (10U)
14252#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
14253#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
14254#define TIM_BDTR_OSSR_Pos (11U)
14255#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
14256#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
14257#define TIM_BDTR_BKE_Pos (12U)
14258#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
14259#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
14260#define TIM_BDTR_BKP_Pos (13U)
14261#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
14262#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
14263#define TIM_BDTR_AOE_Pos (14U)
14264#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
14265#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
14266#define TIM_BDTR_MOE_Pos (15U)
14267#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
14268#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
14269
14270/******************* Bit definition for TIM_DCR register ********************/
14271#define TIM_DCR_DBA_Pos (0U)
14272#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
14273#define TIM_DCR_DBA TIM_DCR_DBA_Msk
14274#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
14275#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
14276#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
14277#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
14278#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
14279
14280#define TIM_DCR_DBL_Pos (8U)
14281#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
14282#define TIM_DCR_DBL TIM_DCR_DBL_Msk
14283#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
14284#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
14285#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
14286#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
14287#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
14288
14289/******************* Bit definition for TIM_DMAR register *******************/
14290#define TIM_DMAR_DMAB_Pos (0U)
14291#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
14292#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
14293
14294/******************* Bit definition for TIM_OR register *********************/
14295#define TIM_OR_TI1_RMP_Pos (0U)
14296#define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos)
14297#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk
14298#define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos)
14299#define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos)
14300
14301#define TIM_OR_TI4_RMP_Pos (6U)
14302#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)
14303#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk
14304#define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)
14305#define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)
14306#define TIM_OR_ITR1_RMP_Pos (10U)
14307#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)
14308#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk
14309#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)
14310#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)
14311
14312
14313/******************************************************************************/
14314/* */
14315/* Universal Synchronous Asynchronous Receiver Transmitter */
14316/* */
14317/******************************************************************************/
14318/******************* Bit definition for USART_SR register *******************/
14319#define USART_SR_PE_Pos (0U)
14320#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)
14321#define USART_SR_PE USART_SR_PE_Msk
14322#define USART_SR_FE_Pos (1U)
14323#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)
14324#define USART_SR_FE USART_SR_FE_Msk
14325#define USART_SR_NE_Pos (2U)
14326#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)
14327#define USART_SR_NE USART_SR_NE_Msk
14328#define USART_SR_ORE_Pos (3U)
14329#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)
14330#define USART_SR_ORE USART_SR_ORE_Msk
14331#define USART_SR_IDLE_Pos (4U)
14332#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)
14333#define USART_SR_IDLE USART_SR_IDLE_Msk
14334#define USART_SR_RXNE_Pos (5U)
14335#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)
14336#define USART_SR_RXNE USART_SR_RXNE_Msk
14337#define USART_SR_TC_Pos (6U)
14338#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)
14339#define USART_SR_TC USART_SR_TC_Msk
14340#define USART_SR_TXE_Pos (7U)
14341#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)
14342#define USART_SR_TXE USART_SR_TXE_Msk
14343#define USART_SR_LBD_Pos (8U)
14344#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)
14345#define USART_SR_LBD USART_SR_LBD_Msk
14346#define USART_SR_CTS_Pos (9U)
14347#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)
14348#define USART_SR_CTS USART_SR_CTS_Msk
14349
14350/******************* Bit definition for USART_DR register *******************/
14351#define USART_DR_DR_Pos (0U)
14352#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)
14353#define USART_DR_DR USART_DR_DR_Msk
14354
14355/****************** Bit definition for USART_BRR register *******************/
14356#define USART_BRR_DIV_Fraction_Pos (0U)
14357#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)
14358#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk
14359#define USART_BRR_DIV_Mantissa_Pos (4U)
14360#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
14361#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk
14362
14363/****************** Bit definition for USART_CR1 register *******************/
14364#define USART_CR1_SBK_Pos (0U)
14365#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)
14366#define USART_CR1_SBK USART_CR1_SBK_Msk
14367#define USART_CR1_RWU_Pos (1U)
14368#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)
14369#define USART_CR1_RWU USART_CR1_RWU_Msk
14370#define USART_CR1_RE_Pos (2U)
14371#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
14372#define USART_CR1_RE USART_CR1_RE_Msk
14373#define USART_CR1_TE_Pos (3U)
14374#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
14375#define USART_CR1_TE USART_CR1_TE_Msk
14376#define USART_CR1_IDLEIE_Pos (4U)
14377#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
14378#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
14379#define USART_CR1_RXNEIE_Pos (5U)
14380#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
14381#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
14382#define USART_CR1_TCIE_Pos (6U)
14383#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
14384#define USART_CR1_TCIE USART_CR1_TCIE_Msk
14385#define USART_CR1_TXEIE_Pos (7U)
14386#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
14387#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
14388#define USART_CR1_PEIE_Pos (8U)
14389#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
14390#define USART_CR1_PEIE USART_CR1_PEIE_Msk
14391#define USART_CR1_PS_Pos (9U)
14392#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
14393#define USART_CR1_PS USART_CR1_PS_Msk
14394#define USART_CR1_PCE_Pos (10U)
14395#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
14396#define USART_CR1_PCE USART_CR1_PCE_Msk
14397#define USART_CR1_WAKE_Pos (11U)
14398#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
14399#define USART_CR1_WAKE USART_CR1_WAKE_Msk
14400#define USART_CR1_M_Pos (12U)
14401#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
14402#define USART_CR1_M USART_CR1_M_Msk
14403#define USART_CR1_UE_Pos (13U)
14404#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
14405#define USART_CR1_UE USART_CR1_UE_Msk
14406#define USART_CR1_OVER8_Pos (15U)
14407#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
14408#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
14409
14410/****************** Bit definition for USART_CR2 register *******************/
14411#define USART_CR2_ADD_Pos (0U)
14412#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)
14413#define USART_CR2_ADD USART_CR2_ADD_Msk
14414#define USART_CR2_LBDL_Pos (5U)
14415#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
14416#define USART_CR2_LBDL USART_CR2_LBDL_Msk
14417#define USART_CR2_LBDIE_Pos (6U)
14418#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
14419#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
14420#define USART_CR2_LBCL_Pos (8U)
14421#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
14422#define USART_CR2_LBCL USART_CR2_LBCL_Msk
14423#define USART_CR2_CPHA_Pos (9U)
14424#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
14425#define USART_CR2_CPHA USART_CR2_CPHA_Msk
14426#define USART_CR2_CPOL_Pos (10U)
14427#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
14428#define USART_CR2_CPOL USART_CR2_CPOL_Msk
14429#define USART_CR2_CLKEN_Pos (11U)
14430#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
14431#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
14432
14433#define USART_CR2_STOP_Pos (12U)
14434#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
14435#define USART_CR2_STOP USART_CR2_STOP_Msk
14436#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
14437#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
14438
14439#define USART_CR2_LINEN_Pos (14U)
14440#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
14441#define USART_CR2_LINEN USART_CR2_LINEN_Msk
14442
14443/****************** Bit definition for USART_CR3 register *******************/
14444#define USART_CR3_EIE_Pos (0U)
14445#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
14446#define USART_CR3_EIE USART_CR3_EIE_Msk
14447#define USART_CR3_IREN_Pos (1U)
14448#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
14449#define USART_CR3_IREN USART_CR3_IREN_Msk
14450#define USART_CR3_IRLP_Pos (2U)
14451#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
14452#define USART_CR3_IRLP USART_CR3_IRLP_Msk
14453#define USART_CR3_HDSEL_Pos (3U)
14454#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
14455#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
14456#define USART_CR3_NACK_Pos (4U)
14457#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
14458#define USART_CR3_NACK USART_CR3_NACK_Msk
14459#define USART_CR3_SCEN_Pos (5U)
14460#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
14461#define USART_CR3_SCEN USART_CR3_SCEN_Msk
14462#define USART_CR3_DMAR_Pos (6U)
14463#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
14464#define USART_CR3_DMAR USART_CR3_DMAR_Msk
14465#define USART_CR3_DMAT_Pos (7U)
14466#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
14467#define USART_CR3_DMAT USART_CR3_DMAT_Msk
14468#define USART_CR3_RTSE_Pos (8U)
14469#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
14470#define USART_CR3_RTSE USART_CR3_RTSE_Msk
14471#define USART_CR3_CTSE_Pos (9U)
14472#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
14473#define USART_CR3_CTSE USART_CR3_CTSE_Msk
14474#define USART_CR3_CTSIE_Pos (10U)
14475#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
14476#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
14477#define USART_CR3_ONEBIT_Pos (11U)
14478#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
14479#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
14480
14481/****************** Bit definition for USART_GTPR register ******************/
14482#define USART_GTPR_PSC_Pos (0U)
14483#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
14484#define USART_GTPR_PSC USART_GTPR_PSC_Msk
14485#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)
14486#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)
14487#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)
14488#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)
14489#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)
14490#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)
14491#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)
14492#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)
14493
14494#define USART_GTPR_GT_Pos (8U)
14495#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
14496#define USART_GTPR_GT USART_GTPR_GT_Msk
14497
14498/******************************************************************************/
14499/* */
14500/* Window WATCHDOG */
14501/* */
14502/******************************************************************************/
14503/******************* Bit definition for WWDG_CR register ********************/
14504#define WWDG_CR_T_Pos (0U)
14505#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
14506#define WWDG_CR_T WWDG_CR_T_Msk
14507#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
14508#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
14509#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
14510#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
14511#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
14512#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
14513#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
14514/* Legacy defines */
14515#define WWDG_CR_T0 WWDG_CR_T_0
14516#define WWDG_CR_T1 WWDG_CR_T_1
14517#define WWDG_CR_T2 WWDG_CR_T_2
14518#define WWDG_CR_T3 WWDG_CR_T_3
14519#define WWDG_CR_T4 WWDG_CR_T_4
14520#define WWDG_CR_T5 WWDG_CR_T_5
14521#define WWDG_CR_T6 WWDG_CR_T_6
14522
14523#define WWDG_CR_WDGA_Pos (7U)
14524#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
14525#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
14526
14527/******************* Bit definition for WWDG_CFR register *******************/
14528#define WWDG_CFR_W_Pos (0U)
14529#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
14530#define WWDG_CFR_W WWDG_CFR_W_Msk
14531#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
14532#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
14533#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
14534#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
14535#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
14536#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
14537#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
14538/* Legacy defines */
14539#define WWDG_CFR_W0 WWDG_CFR_W_0
14540#define WWDG_CFR_W1 WWDG_CFR_W_1
14541#define WWDG_CFR_W2 WWDG_CFR_W_2
14542#define WWDG_CFR_W3 WWDG_CFR_W_3
14543#define WWDG_CFR_W4 WWDG_CFR_W_4
14544#define WWDG_CFR_W5 WWDG_CFR_W_5
14545#define WWDG_CFR_W6 WWDG_CFR_W_6
14546
14547#define WWDG_CFR_WDGTB_Pos (7U)
14548#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
14549#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
14550#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
14551#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
14552/* Legacy defines */
14553#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
14554#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
14555
14556#define WWDG_CFR_EWI_Pos (9U)
14557#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
14558#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
14559
14560/******************* Bit definition for WWDG_SR register ********************/
14561#define WWDG_SR_EWIF_Pos (0U)
14562#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
14563#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
14564
14565
14566/******************************************************************************/
14567/* */
14568/* DBG */
14569/* */
14570/******************************************************************************/
14571/******************** Bit definition for DBGMCU_IDCODE register *************/
14572#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
14573#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
14574#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
14575#define DBGMCU_IDCODE_REV_ID_Pos (16U)
14576#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
14577#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
14578
14579/******************** Bit definition for DBGMCU_CR register *****************/
14580#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
14581#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
14582#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
14583#define DBGMCU_CR_DBG_STOP_Pos (1U)
14584#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
14585#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
14586#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
14587#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
14588#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
14589#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
14590#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
14591#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
14592
14593#define DBGMCU_CR_TRACE_MODE_Pos (6U)
14594#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
14595#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
14596#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
14597#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
14598
14599/******************** Bit definition for DBGMCU_APB1_FZ register ************/
14600#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
14601#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
14602#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
14603#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
14604#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
14605#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
14606#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
14607#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
14608#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
14609#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
14610#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
14611#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
14612#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
14613#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
14614#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
14615#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
14616#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
14617#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
14618#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
14619#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
14620#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
14621#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
14622#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
14623#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
14624#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
14625#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
14626#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
14627#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
14628#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
14629#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
14630#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
14631#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
14632#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
14633#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
14634#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
14635#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
14636#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
14637#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
14638#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
14639#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
14640#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
14641#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
14642#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
14643#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
14644#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
14645#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
14646#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
14647#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
14648#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
14649#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
14650#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
14651/* Old IWDGSTOP bit definition, maintained for legacy purpose */
14652#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
14653
14654/******************** Bit definition for DBGMCU_APB2_FZ register ************/
14655#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
14656#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
14657#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
14658#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
14659#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
14660#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
14661#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
14662#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
14663#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
14664#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
14665#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
14666#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
14667#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
14668#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
14669#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
14670
14671/******************************************************************************/
14672/* */
14673/* Ethernet MAC Registers bits definitions */
14674/* */
14675/******************************************************************************/
14676/* Bit definition for Ethernet MAC Control Register register */
14677#define ETH_MACCR_CSTF_Pos (25U)
14678#define ETH_MACCR_CSTF_Msk (0x1UL << ETH_MACCR_CSTF_Pos)
14679#define ETH_MACCR_CSTF ETH_MACCR_CSTF_Msk /* CRC stripping for Type frames */
14680#define ETH_MACCR_WD_Pos (23U)
14681#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)
14682#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
14683#define ETH_MACCR_JD_Pos (22U)
14684#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)
14685#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
14686#define ETH_MACCR_IFG_Pos (17U)
14687#define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos)
14688#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
14689#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
14690#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
14691#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
14692#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
14693#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
14694#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
14695#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
14696#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
14697#define ETH_MACCR_CSD_Pos (16U)
14698#define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos)
14699#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
14700#define ETH_MACCR_FES_Pos (14U)
14701#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)
14702#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
14703#define ETH_MACCR_ROD_Pos (13U)
14704#define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos)
14705#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
14706#define ETH_MACCR_LM_Pos (12U)
14707#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)
14708#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
14709#define ETH_MACCR_DM_Pos (11U)
14710#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)
14711#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
14712#define ETH_MACCR_IPCO_Pos (10U)
14713#define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos)
14714#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
14715#define ETH_MACCR_RD_Pos (9U)
14716#define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos)
14717#define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
14718#define ETH_MACCR_APCS_Pos (7U)
14719#define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos)
14720#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
14721#define ETH_MACCR_BL_Pos (5U)
14722#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)
14723#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
14724 a transmission attempt during retries after a collision: 0 =< r <2^k */
14725#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
14726#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
14727#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
14728#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
14729#define ETH_MACCR_DC_Pos (4U)
14730#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)
14731#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
14732#define ETH_MACCR_TE_Pos (3U)
14733#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)
14734#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
14735#define ETH_MACCR_RE_Pos (2U)
14736#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)
14737#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
14738
14739/* Bit definition for Ethernet MAC Frame Filter Register */
14740#define ETH_MACFFR_RA_Pos (31U)
14741#define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos)
14742#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
14743#define ETH_MACFFR_HPF_Pos (10U)
14744#define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos)
14745#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
14746#define ETH_MACFFR_SAF_Pos (9U)
14747#define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos)
14748#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
14749#define ETH_MACFFR_SAIF_Pos (8U)
14750#define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos)
14751#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
14752#define ETH_MACFFR_PCF_Pos (6U)
14753#define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos)
14754#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
14755#define ETH_MACFFR_PCF_BlockAll_Pos (6U)
14756#define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos)
14757#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
14758#define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
14759#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos)
14760#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
14761#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
14762#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos)
14763#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
14764#define ETH_MACFFR_BFD_Pos (5U)
14765#define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos)
14766#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
14767#define ETH_MACFFR_PAM_Pos (4U)
14768#define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos)
14769#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
14770#define ETH_MACFFR_DAIF_Pos (3U)
14771#define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos)
14772#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
14773#define ETH_MACFFR_HM_Pos (2U)
14774#define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos)
14775#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
14776#define ETH_MACFFR_HU_Pos (1U)
14777#define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos)
14778#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
14779#define ETH_MACFFR_PM_Pos (0U)
14780#define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos)
14781#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
14782
14783/* Bit definition for Ethernet MAC Hash Table High Register */
14784#define ETH_MACHTHR_HTH_Pos (0U)
14785#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
14786#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
14787
14788/* Bit definition for Ethernet MAC Hash Table Low Register */
14789#define ETH_MACHTLR_HTL_Pos (0U)
14790#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
14791#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
14792
14793/* Bit definition for Ethernet MAC MII Address Register */
14794#define ETH_MACMIIAR_PA_Pos (11U)
14795#define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos)
14796#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
14797#define ETH_MACMIIAR_MR_Pos (6U)
14798#define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos)
14799#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
14800#define ETH_MACMIIAR_CR_Pos (2U)
14801#define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos)
14802#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
14803#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
14804#define ETH_MACMIIAR_CR_Div62_Pos (2U)
14805#define ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos)
14806#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
14807#define ETH_MACMIIAR_CR_Div16_Pos (3U)
14808#define ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos)
14809#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
14810#define ETH_MACMIIAR_CR_Div26_Pos (2U)
14811#define ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos)
14812#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
14813#define ETH_MACMIIAR_CR_Div102_Pos (4U)
14814#define ETH_MACMIIAR_CR_Div102_Msk (0x1UL << ETH_MACMIIAR_CR_Div102_Pos)
14815#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
14816#define ETH_MACMIIAR_MW_Pos (1U)
14817#define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos)
14818#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
14819#define ETH_MACMIIAR_MB_Pos (0U)
14820#define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos)
14821#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
14822
14823/* Bit definition for Ethernet MAC MII Data Register */
14824#define ETH_MACMIIDR_MD_Pos (0U)
14825#define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos)
14826#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
14827
14828/* Bit definition for Ethernet MAC Flow Control Register */
14829#define ETH_MACFCR_PT_Pos (16U)
14830#define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos)
14831#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
14832#define ETH_MACFCR_ZQPD_Pos (7U)
14833#define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos)
14834#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
14835#define ETH_MACFCR_PLT_Pos (4U)
14836#define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos)
14837#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
14838#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
14839#define ETH_MACFCR_PLT_Minus28_Pos (4U)
14840#define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos)
14841#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
14842#define ETH_MACFCR_PLT_Minus144_Pos (5U)
14843#define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos)
14844#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
14845#define ETH_MACFCR_PLT_Minus256_Pos (4U)
14846#define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos)
14847#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
14848#define ETH_MACFCR_UPFD_Pos (3U)
14849#define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos)
14850#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
14851#define ETH_MACFCR_RFCE_Pos (2U)
14852#define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos)
14853#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
14854#define ETH_MACFCR_TFCE_Pos (1U)
14855#define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos)
14856#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
14857#define ETH_MACFCR_FCBBPA_Pos (0U)
14858#define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos)
14859#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
14860
14861/* Bit definition for Ethernet MAC VLAN Tag Register */
14862#define ETH_MACVLANTR_VLANTC_Pos (16U)
14863#define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos)
14864#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
14865#define ETH_MACVLANTR_VLANTI_Pos (0U)
14866#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos)
14867#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
14868
14869/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
14870#define ETH_MACRWUFFR_D_Pos (0U)
14871#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos)
14872#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
14873/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
14874 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
14875/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
14876 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
14877 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
14878 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
14879 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
14880 RSVD - Filter1 Command - RSVD - Filter0 Command
14881 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
14882 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
14883 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
14884
14885/* Bit definition for Ethernet MAC PMT Control and Status Register */
14886#define ETH_MACPMTCSR_WFFRPR_Pos (31U)
14887#define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos)
14888#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
14889#define ETH_MACPMTCSR_GU_Pos (9U)
14890#define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos)
14891#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
14892#define ETH_MACPMTCSR_WFR_Pos (6U)
14893#define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos)
14894#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
14895#define ETH_MACPMTCSR_MPR_Pos (5U)
14896#define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos)
14897#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
14898#define ETH_MACPMTCSR_WFE_Pos (2U)
14899#define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos)
14900#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
14901#define ETH_MACPMTCSR_MPE_Pos (1U)
14902#define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos)
14903#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
14904#define ETH_MACPMTCSR_PD_Pos (0U)
14905#define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos)
14906#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
14907
14908/* Bit definition for Ethernet MAC debug Register */
14909#define ETH_MACDBGR_TFF_Pos (25U)
14910#define ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos)
14911#define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
14912#define ETH_MACDBGR_TFNE_Pos (24U)
14913#define ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos)
14914#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
14915#define ETH_MACDBGR_TFWA_Pos (22U)
14916#define ETH_MACDBGR_TFWA_Msk (0x1UL << ETH_MACDBGR_TFWA_Pos)
14917#define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
14918#define ETH_MACDBGR_TFRS_Pos (20U)
14919#define ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos)
14920#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
14921#define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
14922#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos)
14923#define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
14924#define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
14925#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos)
14926#define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
14927#define ETH_MACDBGR_TFRS_READ_Pos (20U)
14928#define ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos)
14929#define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
14930#define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
14931#define ETH_MACDBGR_MTP_Pos (19U)
14932#define ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos)
14933#define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
14934#define ETH_MACDBGR_MTFCS_Pos (17U)
14935#define ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos)
14936#define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
14937#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
14938#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos)
14939#define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
14940#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
14941#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos)
14942#define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
14943#define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
14944#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos)
14945#define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
14946#define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
14947#define ETH_MACDBGR_MMTEA_Pos (16U)
14948#define ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos)
14949#define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
14950#define ETH_MACDBGR_RFFL_Pos (8U)
14951#define ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos)
14952#define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
14953#define ETH_MACDBGR_RFFL_FULL_Pos (8U)
14954#define ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos)
14955#define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
14956#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
14957#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos)
14958#define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
14959#define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
14960#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos)
14961#define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
14962#define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
14963#define ETH_MACDBGR_RFRCS_Pos (5U)
14964#define ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos)
14965#define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
14966#define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
14967#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos)
14968#define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
14969#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
14970#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos)
14971#define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
14972#define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
14973#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos)
14974#define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
14975#define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
14976#define ETH_MACDBGR_RFWRA_Pos (4U)
14977#define ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos)
14978#define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
14979#define ETH_MACDBGR_MSFRWCS_Pos (1U)
14980#define ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos)
14981#define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
14982#define ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos)
14983#define ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos)
14984#define ETH_MACDBGR_MMRPEA_Pos (0U)
14985#define ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos)
14986#define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
14987
14988/* Bit definition for Ethernet MAC Status Register */
14989#define ETH_MACSR_TSTS_Pos (9U)
14990#define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos)
14991#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
14992#define ETH_MACSR_MMCTS_Pos (6U)
14993#define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos)
14994#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
14995#define ETH_MACSR_MMMCRS_Pos (5U)
14996#define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos)
14997#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
14998#define ETH_MACSR_MMCS_Pos (4U)
14999#define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos)
15000#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
15001#define ETH_MACSR_PMTS_Pos (3U)
15002#define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos)
15003#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
15004
15005/* Bit definition for Ethernet MAC Interrupt Mask Register */
15006#define ETH_MACIMR_TSTIM_Pos (9U)
15007#define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos)
15008#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
15009#define ETH_MACIMR_PMTIM_Pos (3U)
15010#define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos)
15011#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
15012
15013/* Bit definition for Ethernet MAC Address0 High Register */
15014#define ETH_MACA0HR_MACA0H_Pos (0U)
15015#define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos)
15016#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
15017
15018/* Bit definition for Ethernet MAC Address0 Low Register */
15019#define ETH_MACA0LR_MACA0L_Pos (0U)
15020#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos)
15021#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
15022
15023/* Bit definition for Ethernet MAC Address1 High Register */
15024#define ETH_MACA1HR_AE_Pos (31U)
15025#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)
15026#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
15027#define ETH_MACA1HR_SA_Pos (30U)
15028#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)
15029#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
15030#define ETH_MACA1HR_MBC_Pos (24U)
15031#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)
15032#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
15033#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
15034#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
15035#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
15036#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
15037#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
15038#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
15039#define ETH_MACA1HR_MACA1H_Pos (0U)
15040#define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos)
15041#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
15042
15043/* Bit definition for Ethernet MAC Address1 Low Register */
15044#define ETH_MACA1LR_MACA1L_Pos (0U)
15045#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos)
15046#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
15047
15048/* Bit definition for Ethernet MAC Address2 High Register */
15049#define ETH_MACA2HR_AE_Pos (31U)
15050#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)
15051#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
15052#define ETH_MACA2HR_SA_Pos (30U)
15053#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)
15054#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
15055#define ETH_MACA2HR_MBC_Pos (24U)
15056#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)
15057#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
15058#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
15059#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
15060#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
15061#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
15062#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
15063#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
15064#define ETH_MACA2HR_MACA2H_Pos (0U)
15065#define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos)
15066#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
15067
15068/* Bit definition for Ethernet MAC Address2 Low Register */
15069#define ETH_MACA2LR_MACA2L_Pos (0U)
15070#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos)
15071#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
15072
15073/* Bit definition for Ethernet MAC Address3 High Register */
15074#define ETH_MACA3HR_AE_Pos (31U)
15075#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)
15076#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
15077#define ETH_MACA3HR_SA_Pos (30U)
15078#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)
15079#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
15080#define ETH_MACA3HR_MBC_Pos (24U)
15081#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)
15082#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
15083#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
15084#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
15085#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
15086#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
15087#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
15088#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
15089#define ETH_MACA3HR_MACA3H_Pos (0U)
15090#define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos)
15091#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
15092
15093/* Bit definition for Ethernet MAC Address3 Low Register */
15094#define ETH_MACA3LR_MACA3L_Pos (0U)
15095#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos)
15096#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
15097
15098/******************************************************************************/
15099/* Ethernet MMC Registers bits definition */
15100/******************************************************************************/
15101
15102/* Bit definition for Ethernet MMC Control Register */
15103#define ETH_MMCCR_MCFHP_Pos (5U)
15104#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos)
15105#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
15106#define ETH_MMCCR_MCP_Pos (4U)
15107#define ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos)
15108#define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
15109#define ETH_MMCCR_MCF_Pos (3U)
15110#define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos)
15111#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
15112#define ETH_MMCCR_ROR_Pos (2U)
15113#define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos)
15114#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
15115#define ETH_MMCCR_CSR_Pos (1U)
15116#define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos)
15117#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
15118#define ETH_MMCCR_CR_Pos (0U)
15119#define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos)
15120#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
15121
15122/* Bit definition for Ethernet MMC Receive Interrupt Register */
15123#define ETH_MMCRIR_RGUFS_Pos (17U)
15124#define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos)
15125#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
15126#define ETH_MMCRIR_RFAES_Pos (6U)
15127#define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos)
15128#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
15129#define ETH_MMCRIR_RFCES_Pos (5U)
15130#define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos)
15131#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
15132
15133/* Bit definition for Ethernet MMC Transmit Interrupt Register */
15134#define ETH_MMCTIR_TGFS_Pos (21U)
15135#define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos)
15136#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
15137#define ETH_MMCTIR_TGFMSCS_Pos (15U)
15138#define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos)
15139#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
15140#define ETH_MMCTIR_TGFSCS_Pos (14U)
15141#define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos)
15142#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
15143
15144/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
15145#define ETH_MMCRIMR_RGUFM_Pos (17U)
15146#define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos)
15147#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
15148#define ETH_MMCRIMR_RFAEM_Pos (6U)
15149#define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos)
15150#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
15151#define ETH_MMCRIMR_RFCEM_Pos (5U)
15152#define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos)
15153#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
15154
15155/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
15156#define ETH_MMCTIMR_TGFM_Pos (21U)
15157#define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos)
15158#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
15159#define ETH_MMCTIMR_TGFMSCM_Pos (15U)
15160#define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos)
15161#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
15162#define ETH_MMCTIMR_TGFSCM_Pos (14U)
15163#define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos)
15164#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
15165
15166/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
15167#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
15168#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos)
15169#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
15170
15171/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
15172#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
15173#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos)
15174#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
15175
15176/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
15177#define ETH_MMCTGFCR_TGFC_Pos (0U)
15178#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos)
15179#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
15180
15181/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
15182#define ETH_MMCRFCECR_RFCEC_Pos (0U)
15183#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos)
15184#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
15185
15186/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
15187#define ETH_MMCRFAECR_RFAEC_Pos (0U)
15188#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos)
15189#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
15190
15191/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
15192#define ETH_MMCRGUFCR_RGUFC_Pos (0U)
15193#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos)
15194#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
15195
15196/******************************************************************************/
15197/* Ethernet PTP Registers bits definition */
15198/******************************************************************************/
15199
15200/* Bit definition for Ethernet PTP Time Stamp Control Register */
15201#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
15202#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos)
15203#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
15204#define ETH_PTPTSCR_TSCNT_Pos (16U)
15205#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos)
15206#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
15207#define ETH_PTPTSCR_TSSMRME_Pos (15U)
15208#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos)
15209#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
15210#define ETH_PTPTSCR_TSSEME_Pos (14U)
15211#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos)
15212#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
15213#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
15214#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos)
15215#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
15216#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
15217#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos)
15218#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
15219#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
15220#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos)
15221#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
15222#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
15223#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos)
15224#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
15225#define ETH_PTPTSCR_TSSSR_Pos (9U)
15226#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos)
15227#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
15228#define ETH_PTPTSCR_TSSARFE_Pos (8U)
15229#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos)
15230#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
15231
15232#define ETH_PTPTSCR_TSARU_Pos (5U)
15233#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos)
15234#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
15235#define ETH_PTPTSCR_TSITE_Pos (4U)
15236#define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos)
15237#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
15238#define ETH_PTPTSCR_TSSTU_Pos (3U)
15239#define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos)
15240#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
15241#define ETH_PTPTSCR_TSSTI_Pos (2U)
15242#define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos)
15243#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
15244#define ETH_PTPTSCR_TSFCU_Pos (1U)
15245#define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos)
15246#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
15247#define ETH_PTPTSCR_TSE_Pos (0U)
15248#define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos)
15249#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
15250
15251/* Bit definition for Ethernet PTP Sub-Second Increment Register */
15252#define ETH_PTPSSIR_STSSI_Pos (0U)
15253#define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos)
15254#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
15255
15256/* Bit definition for Ethernet PTP Time Stamp High Register */
15257#define ETH_PTPTSHR_STS_Pos (0U)
15258#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos)
15259#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
15260
15261/* Bit definition for Ethernet PTP Time Stamp Low Register */
15262#define ETH_PTPTSLR_STPNS_Pos (31U)
15263#define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos)
15264#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
15265#define ETH_PTPTSLR_STSS_Pos (0U)
15266#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos)
15267#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
15268
15269/* Bit definition for Ethernet PTP Time Stamp High Update Register */
15270#define ETH_PTPTSHUR_TSUS_Pos (0U)
15271#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos)
15272#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
15273
15274/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
15275#define ETH_PTPTSLUR_TSUPNS_Pos (31U)
15276#define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos)
15277#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
15278#define ETH_PTPTSLUR_TSUSS_Pos (0U)
15279#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos)
15280#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
15281
15282/* Bit definition for Ethernet PTP Time Stamp Addend Register */
15283#define ETH_PTPTSAR_TSA_Pos (0U)
15284#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos)
15285#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
15286
15287/* Bit definition for Ethernet PTP Target Time High Register */
15288#define ETH_PTPTTHR_TTSH_Pos (0U)
15289#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos)
15290#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
15291
15292/* Bit definition for Ethernet PTP Target Time Low Register */
15293#define ETH_PTPTTLR_TTSL_Pos (0U)
15294#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos)
15295#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
15296
15297/* Bit definition for Ethernet PTP Time Stamp Status Register */
15298#define ETH_PTPTSSR_TSTTR_Pos (5U)
15299#define ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos)
15300#define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
15301#define ETH_PTPTSSR_TSSO_Pos (4U)
15302#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos)
15303#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
15304
15305/******************************************************************************/
15306/* Ethernet DMA Registers bits definition */
15307/******************************************************************************/
15308
15309/* Bit definition for Ethernet DMA Bus Mode Register */
15310#define ETH_DMABMR_MB_Pos (26U)
15311#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos)
15312#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
15313#define ETH_DMABMR_AAB_Pos (25U)
15314#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos)
15315#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
15316#define ETH_DMABMR_FPM_Pos (24U)
15317#define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos)
15318#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
15319#define ETH_DMABMR_USP_Pos (23U)
15320#define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos)
15321#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
15322#define ETH_DMABMR_RDP_Pos (17U)
15323#define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos)
15324#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
15325#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
15326#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
15327#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
15328#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
15329#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
15330#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
15331#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
15332#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
15333#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
15334#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
15335#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
15336#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
15337#define ETH_DMABMR_FB_Pos (16U)
15338#define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos)
15339#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
15340#define ETH_DMABMR_RTPR_Pos (14U)
15341#define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos)
15342#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
15343#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
15344#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
15345#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
15346#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
15347#define ETH_DMABMR_PBL_Pos (8U)
15348#define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos)
15349#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
15350#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
15351#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
15352#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
15353#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
15354#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
15355#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
15356#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
15357#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
15358#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
15359#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
15360#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
15361#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
15362#define ETH_DMABMR_EDE_Pos (7U)
15363#define ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos)
15364#define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
15365#define ETH_DMABMR_DSL_Pos (2U)
15366#define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos)
15367#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
15368#define ETH_DMABMR_DA_Pos (1U)
15369#define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos)
15370#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
15371#define ETH_DMABMR_SR_Pos (0U)
15372#define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos)
15373#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
15374
15375/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
15376#define ETH_DMATPDR_TPD_Pos (0U)
15377#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos)
15378#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
15379
15380/* Bit definition for Ethernet DMA Receive Poll Demand Register */
15381#define ETH_DMARPDR_RPD_Pos (0U)
15382#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos)
15383#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
15384
15385/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
15386#define ETH_DMARDLAR_SRL_Pos (0U)
15387#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos)
15388#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
15389
15390/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
15391#define ETH_DMATDLAR_STL_Pos (0U)
15392#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos)
15393#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
15394
15395/* Bit definition for Ethernet DMA Status Register */
15396#define ETH_DMASR_TSTS_Pos (29U)
15397#define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos)
15398#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
15399#define ETH_DMASR_PMTS_Pos (28U)
15400#define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos)
15401#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
15402#define ETH_DMASR_MMCS_Pos (27U)
15403#define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos)
15404#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
15405#define ETH_DMASR_EBS_Pos (23U)
15406#define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos)
15407#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
15408/* combination with EBS[2:0] for GetFlagStatus function */
15409#define ETH_DMASR_EBS_DescAccess_Pos (25U)
15410#define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos)
15411#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
15412#define ETH_DMASR_EBS_ReadTransf_Pos (24U)
15413#define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos)
15414#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
15415#define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
15416#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos)
15417#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
15418#define ETH_DMASR_TPS_Pos (20U)
15419#define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos)
15420#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
15421#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
15422#define ETH_DMASR_TPS_Fetching_Pos (20U)
15423#define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos)
15424#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
15425#define ETH_DMASR_TPS_Waiting_Pos (21U)
15426#define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos)
15427#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
15428#define ETH_DMASR_TPS_Reading_Pos (20U)
15429#define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos)
15430#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
15431#define ETH_DMASR_TPS_Suspended_Pos (21U)
15432#define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos)
15433#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
15434#define ETH_DMASR_TPS_Closing_Pos (20U)
15435#define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos)
15436#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
15437#define ETH_DMASR_RPS_Pos (17U)
15438#define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos)
15439#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
15440#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
15441#define ETH_DMASR_RPS_Fetching_Pos (17U)
15442#define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos)
15443#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
15444#define ETH_DMASR_RPS_Waiting_Pos (17U)
15445#define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos)
15446#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
15447#define ETH_DMASR_RPS_Suspended_Pos (19U)
15448#define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos)
15449#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
15450#define ETH_DMASR_RPS_Closing_Pos (17U)
15451#define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos)
15452#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
15453#define ETH_DMASR_RPS_Queuing_Pos (17U)
15454#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos)
15455#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
15456#define ETH_DMASR_NIS_Pos (16U)
15457#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos)
15458#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
15459#define ETH_DMASR_AIS_Pos (15U)
15460#define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos)
15461#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
15462#define ETH_DMASR_ERS_Pos (14U)
15463#define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos)
15464#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
15465#define ETH_DMASR_FBES_Pos (13U)
15466#define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos)
15467#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
15468#define ETH_DMASR_ETS_Pos (10U)
15469#define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos)
15470#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
15471#define ETH_DMASR_RWTS_Pos (9U)
15472#define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos)
15473#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
15474#define ETH_DMASR_RPSS_Pos (8U)
15475#define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos)
15476#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
15477#define ETH_DMASR_RBUS_Pos (7U)
15478#define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos)
15479#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
15480#define ETH_DMASR_RS_Pos (6U)
15481#define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos)
15482#define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
15483#define ETH_DMASR_TUS_Pos (5U)
15484#define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos)
15485#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
15486#define ETH_DMASR_ROS_Pos (4U)
15487#define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos)
15488#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
15489#define ETH_DMASR_TJTS_Pos (3U)
15490#define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos)
15491#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
15492#define ETH_DMASR_TBUS_Pos (2U)
15493#define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos)
15494#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
15495#define ETH_DMASR_TPSS_Pos (1U)
15496#define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos)
15497#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
15498#define ETH_DMASR_TS_Pos (0U)
15499#define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos)
15500#define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
15501
15502/* Bit definition for Ethernet DMA Operation Mode Register */
15503#define ETH_DMAOMR_DTCEFD_Pos (26U)
15504#define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos)
15505#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
15506#define ETH_DMAOMR_RSF_Pos (25U)
15507#define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos)
15508#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
15509#define ETH_DMAOMR_DFRF_Pos (24U)
15510#define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos)
15511#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
15512#define ETH_DMAOMR_TSF_Pos (21U)
15513#define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos)
15514#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
15515#define ETH_DMAOMR_FTF_Pos (20U)
15516#define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos)
15517#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
15518#define ETH_DMAOMR_TTC_Pos (14U)
15519#define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos)
15520#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
15521#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
15522#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
15523#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
15524#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
15525#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
15526#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
15527#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
15528#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
15529#define ETH_DMAOMR_ST_Pos (13U)
15530#define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos)
15531#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
15532#define ETH_DMAOMR_FEF_Pos (7U)
15533#define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos)
15534#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
15535#define ETH_DMAOMR_FUGF_Pos (6U)
15536#define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos)
15537#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
15538#define ETH_DMAOMR_RTC_Pos (3U)
15539#define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos)
15540#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
15541#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
15542#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
15543#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
15544#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
15545#define ETH_DMAOMR_OSF_Pos (2U)
15546#define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos)
15547#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
15548#define ETH_DMAOMR_SR_Pos (1U)
15549#define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos)
15550#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
15551
15552/* Bit definition for Ethernet DMA Interrupt Enable Register */
15553#define ETH_DMAIER_NISE_Pos (16U)
15554#define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos)
15555#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
15556#define ETH_DMAIER_AISE_Pos (15U)
15557#define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos)
15558#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
15559#define ETH_DMAIER_ERIE_Pos (14U)
15560#define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos)
15561#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
15562#define ETH_DMAIER_FBEIE_Pos (13U)
15563#define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos)
15564#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
15565#define ETH_DMAIER_ETIE_Pos (10U)
15566#define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos)
15567#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
15568#define ETH_DMAIER_RWTIE_Pos (9U)
15569#define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos)
15570#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
15571#define ETH_DMAIER_RPSIE_Pos (8U)
15572#define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos)
15573#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
15574#define ETH_DMAIER_RBUIE_Pos (7U)
15575#define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos)
15576#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
15577#define ETH_DMAIER_RIE_Pos (6U)
15578#define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos)
15579#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
15580#define ETH_DMAIER_TUIE_Pos (5U)
15581#define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos)
15582#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
15583#define ETH_DMAIER_ROIE_Pos (4U)
15584#define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos)
15585#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
15586#define ETH_DMAIER_TJTIE_Pos (3U)
15587#define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos)
15588#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
15589#define ETH_DMAIER_TBUIE_Pos (2U)
15590#define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos)
15591#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
15592#define ETH_DMAIER_TPSIE_Pos (1U)
15593#define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos)
15594#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
15595#define ETH_DMAIER_TIE_Pos (0U)
15596#define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos)
15597#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
15598
15599/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
15600#define ETH_DMAMFBOCR_OFOC_Pos (28U)
15601#define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos)
15602#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
15603#define ETH_DMAMFBOCR_MFA_Pos (17U)
15604#define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos)
15605#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
15606#define ETH_DMAMFBOCR_OMFC_Pos (16U)
15607#define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos)
15608#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
15609#define ETH_DMAMFBOCR_MFC_Pos (0U)
15610#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos)
15611#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
15612
15613/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
15614#define ETH_DMACHTDR_HTDAP_Pos (0U)
15615#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos)
15616#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
15617
15618/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
15619#define ETH_DMACHRDR_HRDAP_Pos (0U)
15620#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos)
15621#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
15622
15623/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
15624#define ETH_DMACHTBAR_HTBAP_Pos (0U)
15625#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos)
15626#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
15627
15628/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
15629#define ETH_DMACHRBAR_HRBAP_Pos (0U)
15630#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos)
15631#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
15632
15633/******************************************************************************/
15634/* */
15635/* USB_OTG */
15636/* */
15637/******************************************************************************/
15638/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
15639#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
15640#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
15641#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
15642#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
15643#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
15644#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
15645#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
15646#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
15647#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
15648#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
15649#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
15650#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
15651#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
15652#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
15653#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
15654#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
15655#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
15656#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
15657#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
15658#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
15659#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
15660#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
15661#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
15662#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
15663#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
15664#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
15665#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
15666#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
15667#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos)
15668#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk
15669
15670/******************** Bit definition forUSB_OTG_HCFG register ********************/
15671
15672#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
15673#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
15674#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
15675#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
15676#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
15677#define USB_OTG_HCFG_FSLSS_Pos (2U)
15678#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
15679#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
15680
15681/******************** Bit definition for USB_OTG_DCFG register ********************/
15682
15683#define USB_OTG_DCFG_DSPD_Pos (0U)
15684#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
15685#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
15686#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
15687#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
15688#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
15689#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
15690#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
15691
15692#define USB_OTG_DCFG_DAD_Pos (4U)
15693#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
15694#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
15695#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
15696#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
15697#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
15698#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
15699#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
15700#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
15701#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
15702
15703#define USB_OTG_DCFG_PFIVL_Pos (11U)
15704#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
15705#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
15706#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
15707#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
15708
15709#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
15710#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
15711#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk
15712
15713#define USB_OTG_DCFG_ERRATIM_Pos (15U)
15714#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
15715#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk
15716
15717#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
15718#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
15719#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
15720#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
15721#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
15722
15723/******************** Bit definition for USB_OTG_PCGCR register ********************/
15724#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
15725#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
15726#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
15727#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
15728#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
15729#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
15730#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
15731#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
15732#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
15733
15734/******************** Bit definition for USB_OTG_GOTGINT register ********************/
15735#define USB_OTG_GOTGINT_SEDET_Pos (2U)
15736#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
15737#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
15738#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
15739#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
15740#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
15741#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
15742#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
15743#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
15744#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
15745#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
15746#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
15747#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
15748#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
15749#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
15750#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
15751#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
15752#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
15753
15754/******************** Bit definition for USB_OTG_DCTL register ********************/
15755#define USB_OTG_DCTL_RWUSIG_Pos (0U)
15756#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
15757#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
15758#define USB_OTG_DCTL_SDIS_Pos (1U)
15759#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
15760#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
15761#define USB_OTG_DCTL_GINSTS_Pos (2U)
15762#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
15763#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
15764#define USB_OTG_DCTL_GONSTS_Pos (3U)
15765#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
15766#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
15767
15768#define USB_OTG_DCTL_TCTL_Pos (4U)
15769#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
15770#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
15771#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
15772#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
15773#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
15774#define USB_OTG_DCTL_SGINAK_Pos (7U)
15775#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
15776#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
15777#define USB_OTG_DCTL_CGINAK_Pos (8U)
15778#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
15779#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
15780#define USB_OTG_DCTL_SGONAK_Pos (9U)
15781#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
15782#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
15783#define USB_OTG_DCTL_CGONAK_Pos (10U)
15784#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
15785#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
15786#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
15787#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
15788#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
15789
15790/******************** Bit definition for USB_OTG_HFIR register ********************/
15791#define USB_OTG_HFIR_FRIVL_Pos (0U)
15792#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
15793#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
15794
15795/******************** Bit definition for USB_OTG_HFNUM register ********************/
15796#define USB_OTG_HFNUM_FRNUM_Pos (0U)
15797#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
15798#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
15799#define USB_OTG_HFNUM_FTREM_Pos (16U)
15800#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
15801#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
15802
15803/******************** Bit definition for USB_OTG_DSTS register ********************/
15804#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
15805#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
15806#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
15807
15808#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
15809#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
15810#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
15811#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
15812#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
15813#define USB_OTG_DSTS_EERR_Pos (3U)
15814#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
15815#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
15816#define USB_OTG_DSTS_FNSOF_Pos (8U)
15817#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
15818#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
15819
15820/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
15821#define USB_OTG_GAHBCFG_GINT_Pos (0U)
15822#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
15823#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
15824#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
15825#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
15826#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
15827#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
15828#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
15829#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
15830#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
15831#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
15832#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
15833#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
15834#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
15835#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
15836#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
15837#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
15838#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
15839#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
15840#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
15841
15842/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
15843
15844#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
15845#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
15846#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
15847#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
15848#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
15849#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
15850#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
15851#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
15852#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
15853#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
15854#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
15855#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
15856#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
15857#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
15858#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
15859#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
15860#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
15861#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
15862#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
15863#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
15864#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
15865#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
15866#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
15867#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
15868#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
15869#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
15870#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
15871#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
15872#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
15873#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
15874#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
15875#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
15876#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
15877#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
15878#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
15879#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
15880#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
15881#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
15882#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
15883#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
15884#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
15885#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
15886#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
15887#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
15888#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
15889#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
15890#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
15891#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
15892#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
15893#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
15894#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
15895#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
15896#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
15897#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
15898#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
15899#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
15900#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
15901#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
15902#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
15903#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
15904#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
15905
15906/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
15907#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
15908#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
15909#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
15910#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
15911#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
15912#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
15913#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
15914#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
15915#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
15916#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
15917#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
15918#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
15919#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
15920#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
15921#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
15922
15923
15924#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
15925#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
15926#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
15927#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
15928#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
15929#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
15930#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
15931#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
15932#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
15933#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
15934#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
15935#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
15936#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
15937#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
15938
15939/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
15940#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
15941#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
15942#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
15943#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
15944#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
15945#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
15946#define USB_OTG_DIEPMSK_TOM_Pos (3U)
15947#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
15948#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
15949#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
15950#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
15951#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
15952#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
15953#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
15954#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
15955#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
15956#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
15957#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
15958#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
15959#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
15960#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
15961#define USB_OTG_DIEPMSK_NAKM_Pos (13U)
15962#define USB_OTG_DIEPMSK_NAKM_Msk (0x1UL << USB_OTG_DIEPMSK_NAKM_Pos)
15963#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk
15964
15965/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
15966#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
15967#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
15968#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
15969#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
15970#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15971#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
15972#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15973#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15974#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15975#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15976#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15977#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15978#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15979#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15980
15981#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
15982#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15983#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
15984#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15985#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15986#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15987#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15988#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15989#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15990#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15991#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15992
15993/******************** Bit definition for USB_OTG_HAINT register ********************/
15994#define USB_OTG_HAINT_HAINT_Pos (0U)
15995#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
15996#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
15997
15998/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
15999#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
16000#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
16001#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
16002#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
16003#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
16004#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
16005#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
16006#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
16007#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
16008#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
16009#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
16010#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
16011#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
16012#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
16013#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
16014#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
16015#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
16016#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
16017#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
16018#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
16019#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
16020#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
16021#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
16022#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
16023#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
16024#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
16025#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
16026#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
16027#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
16028#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
16029#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
16030#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
16031#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
16032#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
16033#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
16034#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
16035/******************** Bit definition for USB_OTG_GINTSTS register ********************/
16036#define USB_OTG_GINTSTS_CMOD_Pos (0U)
16037#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
16038#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
16039#define USB_OTG_GINTSTS_MMIS_Pos (1U)
16040#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
16041#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
16042#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
16043#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
16044#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
16045#define USB_OTG_GINTSTS_SOF_Pos (3U)
16046#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
16047#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
16048#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
16049#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
16050#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
16051#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
16052#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
16053#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
16054#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
16055#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
16056#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
16057#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
16058#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
16059#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
16060#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
16061#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
16062#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
16063#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
16064#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
16065#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
16066#define USB_OTG_GINTSTS_USBRST_Pos (12U)
16067#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
16068#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
16069#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
16070#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
16071#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
16072#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
16073#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
16074#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
16075#define USB_OTG_GINTSTS_EOPF_Pos (15U)
16076#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
16077#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
16078#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
16079#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
16080#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
16081#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
16082#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
16083#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
16084#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
16085#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
16086#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
16087#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
16088#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
16089#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
16090#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
16091#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
16092#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
16093#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
16094#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
16095#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
16096#define USB_OTG_GINTSTS_HCINT_Pos (25U)
16097#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
16098#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
16099#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
16100#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
16101#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
16102#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
16103#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
16104#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
16105#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
16106#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
16107#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
16108#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
16109#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
16110#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
16111#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
16112#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
16113#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
16114
16115/******************** Bit definition for USB_OTG_GINTMSK register ********************/
16116#define USB_OTG_GINTMSK_MMISM_Pos (1U)
16117#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
16118#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
16119#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
16120#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
16121#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
16122#define USB_OTG_GINTMSK_SOFM_Pos (3U)
16123#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
16124#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
16125#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
16126#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
16127#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
16128#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
16129#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
16130#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
16131#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
16132#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
16133#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
16134#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
16135#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
16136#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
16137#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
16138#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
16139#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
16140#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
16141#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
16142#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
16143#define USB_OTG_GINTMSK_USBRST_Pos (12U)
16144#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
16145#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
16146#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
16147#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
16148#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
16149#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
16150#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
16151#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
16152#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
16153#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
16154#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
16155#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
16156#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
16157#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
16158#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
16159#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
16160#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
16161#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
16162#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
16163#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
16164#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
16165#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
16166#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
16167#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
16168#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
16169#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
16170#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
16171#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
16172#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
16173#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
16174#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
16175#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
16176#define USB_OTG_GINTMSK_HCIM_Pos (25U)
16177#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
16178#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
16179#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
16180#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
16181#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
16182#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
16183#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
16184#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
16185#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
16186#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
16187#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
16188#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
16189#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
16190#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
16191#define USB_OTG_GINTMSK_WUIM_Pos (31U)
16192#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
16193#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
16194
16195/******************** Bit definition for USB_OTG_DAINT register ********************/
16196#define USB_OTG_DAINT_IEPINT_Pos (0U)
16197#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
16198#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
16199#define USB_OTG_DAINT_OEPINT_Pos (16U)
16200#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
16201#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
16202
16203/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
16204#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
16205#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
16206#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
16207
16208/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
16209#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
16210#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
16211#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
16212#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
16213#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
16214#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
16215#define USB_OTG_GRXSTSP_DPID_Pos (15U)
16216#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
16217#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
16218#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
16219#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
16220#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
16221
16222/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
16223#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
16224#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
16225#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
16226#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
16227#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
16228#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
16229
16230/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
16231#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
16232#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
16233#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
16234
16235/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
16236#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
16237#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
16238#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
16239
16240/******************** Bit definition for OTG register ********************/
16241#define USB_OTG_NPTXFSA_Pos (0U)
16242#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
16243#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
16244#define USB_OTG_NPTXFD_Pos (16U)
16245#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
16246#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
16247#define USB_OTG_TX0FSA_Pos (0U)
16248#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
16249#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
16250#define USB_OTG_TX0FD_Pos (16U)
16251#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
16252#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
16253
16254/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
16255#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
16256#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
16257#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
16258
16259/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
16260#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
16261#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
16262#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
16263
16264#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
16265#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16266#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
16267#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16268#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16269#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16270#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16271#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16272#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16273#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16274#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16275
16276#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
16277#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16278#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
16279#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16280#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16281#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16282#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16283#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16284#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16285#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16286
16287/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
16288#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
16289#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
16290#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
16291#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
16292#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
16293#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
16294
16295#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
16296#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16297#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
16298#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16299#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16300#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16301#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16302#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16303#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16304#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16305#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16306#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16307#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
16308#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
16309#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
16310
16311#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
16312#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16313#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
16314#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16315#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16316#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16317#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16318#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16319#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16320#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16321#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16322#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16323#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
16324#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
16325#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
16326
16327/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
16328#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
16329#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
16330#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
16331
16332/******************** Bit definition for USB_OTG_DEACHINT register ********************/
16333#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
16334#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
16335#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
16336#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
16337#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
16338#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
16339
16340/******************** Bit definition for USB_OTG_GCCFG register ********************/
16341#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
16342#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
16343#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
16344#define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
16345#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos)
16346#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk
16347#define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
16348#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos)
16349#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk
16350#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
16351#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos)
16352#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk
16353#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
16354#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos)
16355#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk
16356#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
16357#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos)
16358#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk
16359
16360/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
16361#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
16362#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
16363#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
16364#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
16365#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
16366#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
16367
16368/******************** Bit definition for USB_OTG_CID register ********************/
16369#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
16370#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
16371#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
16372
16373/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
16374#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
16375#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
16376#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
16377#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
16378#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
16379#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
16380#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
16381#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
16382#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
16383#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
16384#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
16385#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
16386#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
16387#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
16388#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
16389#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
16390#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
16391#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
16392#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
16393#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
16394#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
16395#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
16396#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
16397#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
16398#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
16399#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
16400#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
16401
16402/******************** Bit definition for USB_OTG_HPRT register ********************/
16403#define USB_OTG_HPRT_PCSTS_Pos (0U)
16404#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
16405#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
16406#define USB_OTG_HPRT_PCDET_Pos (1U)
16407#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
16408#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
16409#define USB_OTG_HPRT_PENA_Pos (2U)
16410#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
16411#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
16412#define USB_OTG_HPRT_PENCHNG_Pos (3U)
16413#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
16414#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
16415#define USB_OTG_HPRT_POCA_Pos (4U)
16416#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
16417#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
16418#define USB_OTG_HPRT_POCCHNG_Pos (5U)
16419#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
16420#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
16421#define USB_OTG_HPRT_PRES_Pos (6U)
16422#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
16423#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
16424#define USB_OTG_HPRT_PSUSP_Pos (7U)
16425#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
16426#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
16427#define USB_OTG_HPRT_PRST_Pos (8U)
16428#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
16429#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
16430
16431#define USB_OTG_HPRT_PLSTS_Pos (10U)
16432#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
16433#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
16434#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
16435#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
16436#define USB_OTG_HPRT_PPWR_Pos (12U)
16437#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
16438#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
16439
16440#define USB_OTG_HPRT_PTCTL_Pos (13U)
16441#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
16442#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
16443#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
16444#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
16445#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
16446#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
16447
16448#define USB_OTG_HPRT_PSPD_Pos (17U)
16449#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
16450#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
16451#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
16452#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
16453
16454/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
16455#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
16456#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
16457#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
16458#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
16459#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
16460#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
16461#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
16462#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
16463#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
16464#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
16465#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
16466#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
16467#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
16468#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
16469#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
16470#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
16471#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
16472#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
16473#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
16474#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
16475#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
16476#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
16477#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
16478#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
16479#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
16480#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
16481#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
16482#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
16483#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
16484#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
16485#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
16486#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
16487#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
16488
16489/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
16490#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
16491#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
16492#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
16493#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
16494#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
16495#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
16496
16497/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
16498#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
16499#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
16500#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
16501#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
16502#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
16503#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
16504#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
16505#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
16506#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
16507#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
16508#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
16509#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
16510
16511#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
16512#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
16513#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
16514#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
16515#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
16516#define USB_OTG_DIEPCTL_STALL_Pos (21U)
16517#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
16518#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
16519
16520#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
16521#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
16522#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
16523#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
16524#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
16525#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
16526#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
16527#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
16528#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
16529#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
16530#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
16531#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
16532#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
16533#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
16534#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
16535#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
16536#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
16537#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
16538#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
16539#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
16540#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
16541#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
16542#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
16543#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
16544#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
16545
16546/******************** Bit definition for USB_OTG_HCCHAR register ********************/
16547#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
16548#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
16549#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
16550
16551#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
16552#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
16553#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
16554#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
16555#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
16556#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
16557#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
16558#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
16559#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
16560#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
16561#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
16562#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
16563#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
16564
16565#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
16566#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
16567#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
16568#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
16569#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
16570
16571#define USB_OTG_HCCHAR_MC_Pos (20U)
16572#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
16573#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
16574#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
16575#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
16576
16577#define USB_OTG_HCCHAR_DAD_Pos (22U)
16578#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
16579#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
16580#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
16581#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
16582#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
16583#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
16584#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
16585#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
16586#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
16587#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
16588#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
16589#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
16590#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
16591#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
16592#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
16593#define USB_OTG_HCCHAR_CHENA_Pos (31U)
16594#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
16595#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
16596
16597/******************** Bit definition for USB_OTG_HCSPLT register ********************/
16598
16599#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
16600#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
16601#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
16602#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16603#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16604#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16605#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16606#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16607#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16608#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16609
16610#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
16611#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
16612#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
16613#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16614#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16615#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16616#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16617#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16618#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16619#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16620
16621#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
16622#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
16623#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
16624#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
16625#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
16626#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
16627#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
16628#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
16629#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
16630#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
16631#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
16632
16633/******************** Bit definition for USB_OTG_HCINT register ********************/
16634#define USB_OTG_HCINT_XFRC_Pos (0U)
16635#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
16636#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
16637#define USB_OTG_HCINT_CHH_Pos (1U)
16638#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
16639#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
16640#define USB_OTG_HCINT_AHBERR_Pos (2U)
16641#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
16642#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
16643#define USB_OTG_HCINT_STALL_Pos (3U)
16644#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
16645#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
16646#define USB_OTG_HCINT_NAK_Pos (4U)
16647#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
16648#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
16649#define USB_OTG_HCINT_ACK_Pos (5U)
16650#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
16651#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
16652#define USB_OTG_HCINT_NYET_Pos (6U)
16653#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
16654#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
16655#define USB_OTG_HCINT_TXERR_Pos (7U)
16656#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
16657#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
16658#define USB_OTG_HCINT_BBERR_Pos (8U)
16659#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
16660#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
16661#define USB_OTG_HCINT_FRMOR_Pos (9U)
16662#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
16663#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
16664#define USB_OTG_HCINT_DTERR_Pos (10U)
16665#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
16666#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
16667
16668/******************** Bit definition for USB_OTG_DIEPINT register ********************/
16669#define USB_OTG_DIEPINT_XFRC_Pos (0U)
16670#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
16671#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
16672#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
16673#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
16674#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
16675#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
16676#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
16677#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
16678#define USB_OTG_DIEPINT_TOC_Pos (3U)
16679#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
16680#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
16681#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
16682#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
16683#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
16684#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
16685#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
16686#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
16687#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
16688#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
16689#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
16690#define USB_OTG_DIEPINT_TXFE_Pos (7U)
16691#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
16692#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
16693#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
16694#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
16695#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
16696#define USB_OTG_DIEPINT_BNA_Pos (9U)
16697#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
16698#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
16699#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
16700#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
16701#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
16702#define USB_OTG_DIEPINT_BERR_Pos (12U)
16703#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
16704#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
16705#define USB_OTG_DIEPINT_NAK_Pos (13U)
16706#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
16707#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
16708
16709/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
16710#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
16711#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
16712#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
16713#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
16714#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
16715#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
16716#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
16717#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
16718#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
16719#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
16720#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
16721#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
16722#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
16723#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
16724#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
16725#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
16726#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
16727#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
16728#define USB_OTG_HCINTMSK_NYET_Pos (6U)
16729#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
16730#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
16731#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
16732#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
16733#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
16734#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
16735#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
16736#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
16737#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
16738#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
16739#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
16740#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
16741#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
16742#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
16743
16744/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
16745
16746#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
16747#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
16748#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
16749#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
16750#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
16751#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
16752#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
16753#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
16754#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
16755/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
16756#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
16757#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
16758#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
16759#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
16760#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
16761#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
16762#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
16763#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
16764#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
16765#define USB_OTG_HCTSIZ_DPID_Pos (29U)
16766#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
16767#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
16768#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
16769#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
16770
16771/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
16772#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
16773#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
16774#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
16775
16776/******************** Bit definition for USB_OTG_HCDMA register ********************/
16777#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
16778#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
16779#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
16780
16781/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
16782#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
16783#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
16784#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
16785
16786/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
16787#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
16788#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
16789#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
16790#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
16791#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
16792#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
16793
16794/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
16795
16796#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
16797#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
16798#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
16799#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
16800#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
16801#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
16802#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
16803#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
16804#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
16805#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
16806#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
16807#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
16808#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
16809#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
16810#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
16811#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
16812#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
16813#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
16814#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
16815#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
16816#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
16817#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
16818#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
16819#define USB_OTG_DOEPCTL_STALL_Pos (21U)
16820#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
16821#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
16822#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
16823#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
16824#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
16825#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
16826#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
16827#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
16828#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
16829#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
16830#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
16831#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
16832#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
16833#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
16834
16835/******************** Bit definition for USB_OTG_DOEPINT register ********************/
16836#define USB_OTG_DOEPINT_XFRC_Pos (0U)
16837#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
16838#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
16839#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
16840#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
16841#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
16842#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
16843#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
16844#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
16845#define USB_OTG_DOEPINT_STUP_Pos (3U)
16846#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
16847#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
16848#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
16849#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
16850#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
16851#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
16852#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
16853#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
16854#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
16855#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
16856#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
16857#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
16858#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
16859#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
16860#define USB_OTG_DOEPINT_NAK_Pos (13U)
16861#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
16862#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
16863#define USB_OTG_DOEPINT_NYET_Pos (14U)
16864#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
16865#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
16866#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
16867#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
16868#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
16869/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
16870
16871#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
16872#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
16873#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
16874#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
16875#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
16876#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
16877
16878#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
16879#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
16880#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
16881#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
16882#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
16883
16884/******************** Bit definition for PCGCCTL register ********************/
16885#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
16886#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
16887#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
16888#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
16889#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
16890#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
16891#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
16892#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
16893#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
16894
16895/* Legacy define */
16896/******************** Bit definition for OTG register ********************/
16897#define USB_OTG_CHNUM_Pos (0U)
16898#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
16899#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
16900#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
16901#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
16902#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
16903#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
16904#define USB_OTG_BCNT_Pos (4U)
16905#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
16906#define USB_OTG_BCNT USB_OTG_BCNT_Msk
16907
16908#define USB_OTG_DPID_Pos (15U)
16909#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
16910#define USB_OTG_DPID USB_OTG_DPID_Msk
16911#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
16912#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
16913
16914#define USB_OTG_PKTSTS_Pos (17U)
16915#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
16916#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
16917#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
16918#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
16919#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
16920#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
16921
16922#define USB_OTG_EPNUM_Pos (0U)
16923#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
16924#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
16925#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
16926#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
16927#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
16928#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
16929
16930#define USB_OTG_FRMNUM_Pos (21U)
16931#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
16932#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
16933#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
16934#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
16935#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
16936#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
16940
16944
16948
16949/******************************* ADC Instances ********************************/
16950#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
16951 ((INSTANCE) == ADC2) || \
16952 ((INSTANCE) == ADC3))
16953
16954#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
16955
16956#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
16957
16958/******************************* CAN Instances ********************************/
16959#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
16960 ((INSTANCE) == CAN2))
16961/******************************* CRC Instances ********************************/
16962#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
16963
16964/******************************* DAC Instances ********************************/
16965#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
16966
16967/******************************* DCMI Instances *******************************/
16968#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
16969
16970/******************************* DMA2D Instances *******************************/
16971#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
16972
16973/******************************** DMA Instances *******************************/
16974#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
16975 ((INSTANCE) == DMA1_Stream1) || \
16976 ((INSTANCE) == DMA1_Stream2) || \
16977 ((INSTANCE) == DMA1_Stream3) || \
16978 ((INSTANCE) == DMA1_Stream4) || \
16979 ((INSTANCE) == DMA1_Stream5) || \
16980 ((INSTANCE) == DMA1_Stream6) || \
16981 ((INSTANCE) == DMA1_Stream7) || \
16982 ((INSTANCE) == DMA2_Stream0) || \
16983 ((INSTANCE) == DMA2_Stream1) || \
16984 ((INSTANCE) == DMA2_Stream2) || \
16985 ((INSTANCE) == DMA2_Stream3) || \
16986 ((INSTANCE) == DMA2_Stream4) || \
16987 ((INSTANCE) == DMA2_Stream5) || \
16988 ((INSTANCE) == DMA2_Stream6) || \
16989 ((INSTANCE) == DMA2_Stream7))
16990
16991/******************************* GPIO Instances *******************************/
16992#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
16993 ((INSTANCE) == GPIOB) || \
16994 ((INSTANCE) == GPIOC) || \
16995 ((INSTANCE) == GPIOD) || \
16996 ((INSTANCE) == GPIOE) || \
16997 ((INSTANCE) == GPIOF) || \
16998 ((INSTANCE) == GPIOG) || \
16999 ((INSTANCE) == GPIOH) || \
17000 ((INSTANCE) == GPIOI) || \
17001 ((INSTANCE) == GPIOJ) || \
17002 ((INSTANCE) == GPIOK))
17003
17004/******************************** I2C Instances *******************************/
17005#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
17006 ((INSTANCE) == I2C2) || \
17007 ((INSTANCE) == I2C3))
17008
17009/******************************* SMBUS Instances ******************************/
17010#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
17011
17012/******************************** I2S Instances *******************************/
17013
17014#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
17015 ((INSTANCE) == SPI3))
17016
17017/*************************** I2S Extended Instances ***************************/
17018#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
17019 ((INSTANCE) == I2S3ext))
17020/* Legacy Defines */
17021#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
17022
17023/****************************** LTDC Instances ********************************/
17024#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
17025/******************************* RNG Instances ********************************/
17026#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
17027
17028/****************************** RTC Instances *********************************/
17029#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
17030
17031/******************************* SAI Instances ********************************/
17032#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
17033 ((PERIPH) == SAI1_Block_B))
17034/* Legacy define */
17035
17036#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
17037
17038/******************************** SPI Instances *******************************/
17039#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
17040 ((INSTANCE) == SPI2) || \
17041 ((INSTANCE) == SPI3) || \
17042 ((INSTANCE) == SPI4) || \
17043 ((INSTANCE) == SPI5) || \
17044 ((INSTANCE) == SPI6))
17045
17046
17047/****************** TIM Instances : All supported instances *******************/
17048#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17049 ((INSTANCE) == TIM2) || \
17050 ((INSTANCE) == TIM3) || \
17051 ((INSTANCE) == TIM4) || \
17052 ((INSTANCE) == TIM5) || \
17053 ((INSTANCE) == TIM6) || \
17054 ((INSTANCE) == TIM7) || \
17055 ((INSTANCE) == TIM8) || \
17056 ((INSTANCE) == TIM9) || \
17057 ((INSTANCE) == TIM10)|| \
17058 ((INSTANCE) == TIM11)|| \
17059 ((INSTANCE) == TIM12)|| \
17060 ((INSTANCE) == TIM13)|| \
17061 ((INSTANCE) == TIM14))
17062
17063/************* TIM Instances : at least 1 capture/compare channel *************/
17064#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17065 ((INSTANCE) == TIM2) || \
17066 ((INSTANCE) == TIM3) || \
17067 ((INSTANCE) == TIM4) || \
17068 ((INSTANCE) == TIM5) || \
17069 ((INSTANCE) == TIM8) || \
17070 ((INSTANCE) == TIM9) || \
17071 ((INSTANCE) == TIM10) || \
17072 ((INSTANCE) == TIM11) || \
17073 ((INSTANCE) == TIM12) || \
17074 ((INSTANCE) == TIM13) || \
17075 ((INSTANCE) == TIM14))
17076
17077/************ TIM Instances : at least 2 capture/compare channels *************/
17078#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17079 ((INSTANCE) == TIM2) || \
17080 ((INSTANCE) == TIM3) || \
17081 ((INSTANCE) == TIM4) || \
17082 ((INSTANCE) == TIM5) || \
17083 ((INSTANCE) == TIM8) || \
17084 ((INSTANCE) == TIM9) || \
17085 ((INSTANCE) == TIM12))
17086
17087/************ TIM Instances : at least 3 capture/compare channels *************/
17088#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17089 ((INSTANCE) == TIM2) || \
17090 ((INSTANCE) == TIM3) || \
17091 ((INSTANCE) == TIM4) || \
17092 ((INSTANCE) == TIM5) || \
17093 ((INSTANCE) == TIM8))
17094
17095/************ TIM Instances : at least 4 capture/compare channels *************/
17096#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17097 ((INSTANCE) == TIM2) || \
17098 ((INSTANCE) == TIM3) || \
17099 ((INSTANCE) == TIM4) || \
17100 ((INSTANCE) == TIM5) || \
17101 ((INSTANCE) == TIM8))
17102
17103/******************** TIM Instances : Advanced-control timers *****************/
17104#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17105 ((INSTANCE) == TIM8))
17106
17107/******************* TIM Instances : Timer input XOR function *****************/
17108#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17109 ((INSTANCE) == TIM2) || \
17110 ((INSTANCE) == TIM3) || \
17111 ((INSTANCE) == TIM4) || \
17112 ((INSTANCE) == TIM5) || \
17113 ((INSTANCE) == TIM8))
17114
17115/****************** TIM Instances : DMA requests generation (UDE) *************/
17116#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17117 ((INSTANCE) == TIM2) || \
17118 ((INSTANCE) == TIM3) || \
17119 ((INSTANCE) == TIM4) || \
17120 ((INSTANCE) == TIM5) || \
17121 ((INSTANCE) == TIM6) || \
17122 ((INSTANCE) == TIM7) || \
17123 ((INSTANCE) == TIM8))
17124
17125/************ TIM Instances : DMA requests generation (CCxDE) *****************/
17126#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17127 ((INSTANCE) == TIM2) || \
17128 ((INSTANCE) == TIM3) || \
17129 ((INSTANCE) == TIM4) || \
17130 ((INSTANCE) == TIM5) || \
17131 ((INSTANCE) == TIM8))
17132
17133/************ TIM Instances : DMA requests generation (COMDE) *****************/
17134#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17135 ((INSTANCE) == TIM2) || \
17136 ((INSTANCE) == TIM3) || \
17137 ((INSTANCE) == TIM4) || \
17138 ((INSTANCE) == TIM5) || \
17139 ((INSTANCE) == TIM8))
17140
17141/******************** TIM Instances : DMA burst feature ***********************/
17142#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17143 ((INSTANCE) == TIM2) || \
17144 ((INSTANCE) == TIM3) || \
17145 ((INSTANCE) == TIM4) || \
17146 ((INSTANCE) == TIM5) || \
17147 ((INSTANCE) == TIM8))
17148
17149/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
17150#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17151 ((INSTANCE) == TIM2) || \
17152 ((INSTANCE) == TIM3) || \
17153 ((INSTANCE) == TIM4) || \
17154 ((INSTANCE) == TIM5) || \
17155 ((INSTANCE) == TIM6) || \
17156 ((INSTANCE) == TIM7) || \
17157 ((INSTANCE) == TIM8))
17158
17159/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
17160#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17161 ((INSTANCE) == TIM2) || \
17162 ((INSTANCE) == TIM3) || \
17163 ((INSTANCE) == TIM4) || \
17164 ((INSTANCE) == TIM5) || \
17165 ((INSTANCE) == TIM8) || \
17166 ((INSTANCE) == TIM9) || \
17167 ((INSTANCE) == TIM12))
17168/********************** TIM Instances : 32 bit Counter ************************/
17169#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
17170 ((INSTANCE) == TIM5))
17171
17172/***************** TIM Instances : external trigger input available ************/
17173#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17174 ((INSTANCE) == TIM2) || \
17175 ((INSTANCE) == TIM3) || \
17176 ((INSTANCE) == TIM4) || \
17177 ((INSTANCE) == TIM5) || \
17178 ((INSTANCE) == TIM8))
17179
17180/****************** TIM Instances : remapping capability **********************/
17181#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
17182 ((INSTANCE) == TIM5) || \
17183 ((INSTANCE) == TIM11))
17184
17185/******************* TIM Instances : output(s) available **********************/
17186#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
17187 ((((INSTANCE) == TIM1) && \
17188 (((CHANNEL) == TIM_CHANNEL_1) || \
17189 ((CHANNEL) == TIM_CHANNEL_2) || \
17190 ((CHANNEL) == TIM_CHANNEL_3) || \
17191 ((CHANNEL) == TIM_CHANNEL_4))) \
17192 || \
17193 (((INSTANCE) == TIM2) && \
17194 (((CHANNEL) == TIM_CHANNEL_1) || \
17195 ((CHANNEL) == TIM_CHANNEL_2) || \
17196 ((CHANNEL) == TIM_CHANNEL_3) || \
17197 ((CHANNEL) == TIM_CHANNEL_4))) \
17198 || \
17199 (((INSTANCE) == TIM3) && \
17200 (((CHANNEL) == TIM_CHANNEL_1) || \
17201 ((CHANNEL) == TIM_CHANNEL_2) || \
17202 ((CHANNEL) == TIM_CHANNEL_3) || \
17203 ((CHANNEL) == TIM_CHANNEL_4))) \
17204 || \
17205 (((INSTANCE) == TIM4) && \
17206 (((CHANNEL) == TIM_CHANNEL_1) || \
17207 ((CHANNEL) == TIM_CHANNEL_2) || \
17208 ((CHANNEL) == TIM_CHANNEL_3) || \
17209 ((CHANNEL) == TIM_CHANNEL_4))) \
17210 || \
17211 (((INSTANCE) == TIM5) && \
17212 (((CHANNEL) == TIM_CHANNEL_1) || \
17213 ((CHANNEL) == TIM_CHANNEL_2) || \
17214 ((CHANNEL) == TIM_CHANNEL_3) || \
17215 ((CHANNEL) == TIM_CHANNEL_4))) \
17216 || \
17217 (((INSTANCE) == TIM8) && \
17218 (((CHANNEL) == TIM_CHANNEL_1) || \
17219 ((CHANNEL) == TIM_CHANNEL_2) || \
17220 ((CHANNEL) == TIM_CHANNEL_3) || \
17221 ((CHANNEL) == TIM_CHANNEL_4))) \
17222 || \
17223 (((INSTANCE) == TIM9) && \
17224 (((CHANNEL) == TIM_CHANNEL_1) || \
17225 ((CHANNEL) == TIM_CHANNEL_2))) \
17226 || \
17227 (((INSTANCE) == TIM10) && \
17228 (((CHANNEL) == TIM_CHANNEL_1))) \
17229 || \
17230 (((INSTANCE) == TIM11) && \
17231 (((CHANNEL) == TIM_CHANNEL_1))) \
17232 || \
17233 (((INSTANCE) == TIM12) && \
17234 (((CHANNEL) == TIM_CHANNEL_1) || \
17235 ((CHANNEL) == TIM_CHANNEL_2))) \
17236 || \
17237 (((INSTANCE) == TIM13) && \
17238 (((CHANNEL) == TIM_CHANNEL_1))) \
17239 || \
17240 (((INSTANCE) == TIM14) && \
17241 (((CHANNEL) == TIM_CHANNEL_1))))
17242
17243/************ TIM Instances : complementary output(s) available ***************/
17244#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
17245 ((((INSTANCE) == TIM1) && \
17246 (((CHANNEL) == TIM_CHANNEL_1) || \
17247 ((CHANNEL) == TIM_CHANNEL_2) || \
17248 ((CHANNEL) == TIM_CHANNEL_3))) \
17249 || \
17250 (((INSTANCE) == TIM8) && \
17251 (((CHANNEL) == TIM_CHANNEL_1) || \
17252 ((CHANNEL) == TIM_CHANNEL_2) || \
17253 ((CHANNEL) == TIM_CHANNEL_3))))
17254
17255/****************** TIM Instances : supporting counting mode selection ********/
17256#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17257 ((INSTANCE) == TIM2) || \
17258 ((INSTANCE) == TIM3) || \
17259 ((INSTANCE) == TIM4) || \
17260 ((INSTANCE) == TIM5) || \
17261 ((INSTANCE) == TIM8))
17262
17263/****************** TIM Instances : supporting clock division *****************/
17264#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17265 ((INSTANCE) == TIM2) || \
17266 ((INSTANCE) == TIM3) || \
17267 ((INSTANCE) == TIM4) || \
17268 ((INSTANCE) == TIM5) || \
17269 ((INSTANCE) == TIM8) || \
17270 ((INSTANCE) == TIM9) || \
17271 ((INSTANCE) == TIM10)|| \
17272 ((INSTANCE) == TIM11)|| \
17273 ((INSTANCE) == TIM12)|| \
17274 ((INSTANCE) == TIM13)|| \
17275 ((INSTANCE) == TIM14))
17276
17277/****************** TIM Instances : supporting commutation event generation ***/
17278#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
17279 ((INSTANCE) == TIM8))
17280
17281
17282/****************** TIM Instances : supporting OCxREF clear *******************/
17283#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17284 ((INSTANCE) == TIM2) || \
17285 ((INSTANCE) == TIM3) || \
17286 ((INSTANCE) == TIM4) || \
17287 ((INSTANCE) == TIM5) || \
17288 ((INSTANCE) == TIM8))
17289
17290/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
17291#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17292 ((INSTANCE) == TIM2) || \
17293 ((INSTANCE) == TIM3) || \
17294 ((INSTANCE) == TIM4) || \
17295 ((INSTANCE) == TIM5) || \
17296 ((INSTANCE) == TIM8) || \
17297 ((INSTANCE) == TIM9) || \
17298 ((INSTANCE) == TIM12))
17299
17300/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
17301#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17302 ((INSTANCE) == TIM2) || \
17303 ((INSTANCE) == TIM3) || \
17304 ((INSTANCE) == TIM4) || \
17305 ((INSTANCE) == TIM5) || \
17306 ((INSTANCE) == TIM8))
17307
17308/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
17309#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17310 ((INSTANCE) == TIM2) || \
17311 ((INSTANCE) == TIM3) || \
17312 ((INSTANCE) == TIM4) || \
17313 ((INSTANCE) == TIM5) || \
17314 ((INSTANCE) == TIM8) || \
17315 ((INSTANCE) == TIM9) || \
17316 ((INSTANCE) == TIM12))
17317
17318/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
17319#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17320 ((INSTANCE) == TIM2) || \
17321 ((INSTANCE) == TIM3) || \
17322 ((INSTANCE) == TIM4) || \
17323 ((INSTANCE) == TIM5) || \
17324 ((INSTANCE) == TIM8) || \
17325 ((INSTANCE) == TIM9) || \
17326 ((INSTANCE) == TIM12))
17327
17328/****************** TIM Instances : supporting repetition counter *************/
17329#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17330 ((INSTANCE) == TIM8))
17331
17332/****************** TIM Instances : supporting encoder interface **************/
17333#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17334 ((INSTANCE) == TIM2) || \
17335 ((INSTANCE) == TIM3) || \
17336 ((INSTANCE) == TIM4) || \
17337 ((INSTANCE) == TIM5) || \
17338 ((INSTANCE) == TIM8) || \
17339 ((INSTANCE) == TIM9) || \
17340 ((INSTANCE) == TIM12))
17341/****************** TIM Instances : supporting Hall sensor interface **********/
17342#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17343 ((INSTANCE) == TIM2) || \
17344 ((INSTANCE) == TIM3) || \
17345 ((INSTANCE) == TIM4) || \
17346 ((INSTANCE) == TIM5) || \
17347 ((INSTANCE) == TIM8))
17348/****************** TIM Instances : supporting the break function *************/
17349#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17350 ((INSTANCE) == TIM8))
17351
17352/******************** USART Instances : Synchronous mode **********************/
17353#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17354 ((INSTANCE) == USART2) || \
17355 ((INSTANCE) == USART3) || \
17356 ((INSTANCE) == USART6))
17357
17358/******************** UART Instances : Half-Duplex mode **********************/
17359#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17360 ((INSTANCE) == USART2) || \
17361 ((INSTANCE) == USART3) || \
17362 ((INSTANCE) == UART4) || \
17363 ((INSTANCE) == UART5) || \
17364 ((INSTANCE) == USART6) || \
17365 ((INSTANCE) == UART7) || \
17366 ((INSTANCE) == UART8))
17367
17368/* Legacy defines */
17369#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
17370
17371/****************** UART Instances : Hardware Flow control ********************/
17372#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17373 ((INSTANCE) == USART2) || \
17374 ((INSTANCE) == USART3) || \
17375 ((INSTANCE) == USART6))
17376/******************** UART Instances : LIN mode **********************/
17377#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
17378
17379/********************* UART Instances : Smart card mode ***********************/
17380#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17381 ((INSTANCE) == USART2) || \
17382 ((INSTANCE) == USART3) || \
17383 ((INSTANCE) == USART6))
17384
17385/*********************** UART Instances : IRDA mode ***************************/
17386#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17387 ((INSTANCE) == USART2) || \
17388 ((INSTANCE) == USART3) || \
17389 ((INSTANCE) == UART4) || \
17390 ((INSTANCE) == UART5) || \
17391 ((INSTANCE) == USART6) || \
17392 ((INSTANCE) == UART7) || \
17393 ((INSTANCE) == UART8))
17394
17395/*********************** PCD Instances ****************************************/
17396#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
17397 ((INSTANCE) == USB_OTG_HS))
17398
17399/*********************** HCD Instances ****************************************/
17400#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
17401 ((INSTANCE) == USB_OTG_HS))
17402
17403/****************************** SDIO Instances ********************************/
17404#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
17405
17406/****************************** IWDG Instances ********************************/
17407#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
17408
17409/****************************** WWDG Instances ********************************/
17410#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
17411
17412/****************************** USB Exported Constants ************************/
17413#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
17414#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
17415#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
17416#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
17417
17418/*
17419 * @brief Specific devices reset values definitions
17420 */
17421#define RCC_PLLCFGR_RST_VALUE 0x24003010U
17422#define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
17423#define RCC_PLLSAICFGR_RST_VALUE 0x24003000U
17424
17425#define RCC_MAX_FREQUENCY 180000000U
17426#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY
17427#define RCC_MAX_FREQUENCY_SCALE2 168000000U
17428#define RCC_MAX_FREQUENCY_SCALE3 120000000U
17429#define RCC_PLLVCO_OUTPUT_MIN 100000000U
17430#define RCC_PLLVCO_INPUT_MIN 950000U
17431#define RCC_PLLVCO_INPUT_MAX 2100000U
17432#define RCC_PLLVCO_OUTPUT_MAX 432000000U
17433
17434#define RCC_PLLN_MIN_VALUE 50U
17435#define RCC_PLLN_MAX_VALUE 432U
17436
17437#define FLASH_SCALE1_LATENCY1_FREQ 30000000U
17438#define FLASH_SCALE1_LATENCY2_FREQ 60000000U
17439#define FLASH_SCALE1_LATENCY3_FREQ 90000000U
17440#define FLASH_SCALE1_LATENCY4_FREQ 120000000U
17441#define FLASH_SCALE1_LATENCY5_FREQ 150000000U
17442
17443#define FLASH_SCALE2_LATENCY1_FREQ 30000000U
17444#define FLASH_SCALE2_LATENCY2_FREQ 60000000U
17445#define FLASH_SCALE2_LATENCY3_FREQ 90000000U
17446#define FLASH_SCALE2_LATENCY4_FREQ 120000000U
17447#define FLASH_SCALE2_LATENCY5_FREQ 150000000U
17448
17449#define FLASH_SCALE3_LATENCY1_FREQ 30000000U
17450#define FLASH_SCALE3_LATENCY2_FREQ 60000000U
17451#define FLASH_SCALE3_LATENCY3_FREQ 90000000U
17452
17453#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
17454#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
17455#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
17456#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
17457/******************************************************************************/
17458/* For a painless codes migration between the STM32F4xx device product */
17459/* lines, the aliases defined below are put in place to overcome the */
17460/* differences in the interrupt handlers and IRQn definitions. */
17461/* No need to update developed interrupt code when moving across */
17462/* product lines within the same STM32F4 Family */
17463/******************************************************************************/
17464/* Aliases for __IRQn */
17465#define FSMC_IRQn FMC_IRQn
17466
17467/* Aliases for __IRQHandler */
17468#define FSMC_IRQHandler FMC_IRQHandler
17469
17473
17477
17481
17482#ifdef __cplusplus
17483}
17484#endif /* __cplusplus */
17485
17486#endif /* __STM32F439xx_H */
__IO
#define __IO
Definition core_armv81mml.h:290
RESERVED
#define RESERVED(N, T)
Definition core_ca.h:179
FMC_IRQn
#define FMC_IRQn
Definition stm32f405xx.h:14292
HASH_RNG_IRQn
#define HASH_RNG_IRQn
Definition stm32f405xx.h:157
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f401xc.h:66
PendSV_IRQn
@ PendSV_IRQn
Definition stm32f401xc.h:74
ETH_WKUP_IRQn
@ ETH_WKUP_IRQn
Definition stm32f407xx.h:139
EXTI2_IRQn
@ EXTI2_IRQn
Definition stm32f401xc.h:85
DMA1_Stream2_IRQn
@ DMA1_Stream2_IRQn
Definition stm32f401xc.h:90
CAN1_SCE_IRQn
@ CAN1_SCE_IRQn
Definition stm32f405xx.h:99
SDIO_IRQn
@ SDIO_IRQn
Definition stm32f401xc.h:116
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition stm32f401xc.h:80
OTG_HS_EP1_IN_IRQn
@ OTG_HS_EP1_IN_IRQn
Definition stm32f405xx.h:150
DMA2_Stream0_IRQn
@ DMA2_Stream0_IRQn
Definition stm32f401xc.h:119
DMA2_Stream6_IRQn
@ DMA2_Stream6_IRQn
Definition stm32f401xc.h:126
UART7_IRQn
@ UART7_IRQn
Definition stm32f413xx.h:156
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition stm32f401xc.h:105
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition stm32f401xc.h:106
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition stm32f401xc.h:69
SAI1_IRQn
@ SAI1_IRQn
Definition stm32f413xx.h:160
TIM4_IRQn
@ TIM4_IRQn
Definition stm32f401xc.h:103
TIM2_IRQn
@ TIM2_IRQn
Definition stm32f401xc.h:101
LTDC_ER_IRQn
@ LTDC_ER_IRQn
Definition stm32f429xx.h:165
DMA2_Stream7_IRQn
@ DMA2_Stream7_IRQn
Definition stm32f401xc.h:127
TIM8_BRK_TIM12_IRQn
@ TIM8_BRK_TIM12_IRQn
Definition stm32f405xx.h:120
USART2_IRQn
@ USART2_IRQn
Definition stm32f401xc.h:111
DMA2_Stream3_IRQn
@ DMA2_Stream3_IRQn
Definition stm32f401xc.h:122
SVCall_IRQn
@ SVCall_IRQn
Definition stm32f401xc.h:72
ADC_IRQn
@ ADC_IRQn
Definition stm32f401xc.h:95
SPI3_IRQn
@ SPI3_IRQn
Definition stm32f401xc.h:118
SPI2_IRQn
@ SPI2_IRQn
Definition stm32f401xc.h:109
TIM7_IRQn
@ TIM7_IRQn
Definition stm32f405xx.h:132
UART8_IRQn
@ UART8_IRQn
Definition stm32f413xx.h:157
CAN2_SCE_IRQn
@ CAN2_SCE_IRQn
Definition stm32f405xx.h:141
RCC_IRQn
@ RCC_IRQn
Definition stm32f401xc.h:82
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition stm32f405xx.h:131
OTG_HS_EP1_OUT_IRQn
@ OTG_HS_EP1_OUT_IRQn
Definition stm32f405xx.h:149
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition stm32f401xc.h:107
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition stm32f405xx.h:123
UsageFault_IRQn
@ UsageFault_IRQn
Definition stm32f401xc.h:71
SysTick_IRQn
@ SysTick_IRQn
Definition stm32f401xc.h:75
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition stm32f401xc.h:130
CRYP_IRQn
@ CRYP_IRQn
Definition stm32f415xx.h:153
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition stm32f401xc.h:129
CAN2_RX0_IRQn
@ CAN2_RX0_IRQn
Definition stm32f405xx.h:139
BusFault_IRQn
@ BusFault_IRQn
Definition stm32f401xc.h:70
SPI5_IRQn
@ SPI5_IRQn
Definition stm32f410cx.h:125
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition stm32f401xc.h:73
FLASH_IRQn
@ FLASH_IRQn
Definition stm32f401xc.h:81
DMA2_Stream5_IRQn
@ DMA2_Stream5_IRQn
Definition stm32f401xc.h:125
WWDG_IRQn
@ WWDG_IRQn
Definition stm32f401xc.h:77
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition stm32f401xc.h:104
TIM3_IRQn
@ TIM3_IRQn
Definition stm32f401xc.h:102
DMA2_Stream1_IRQn
@ DMA2_Stream1_IRQn
Definition stm32f401xc.h:120
CAN1_TX_IRQn
@ CAN1_TX_IRQn
Definition stm32f405xx.h:96
OTG_HS_WKUP_IRQn
@ OTG_HS_WKUP_IRQn
Definition stm32f405xx.h:151
DMA1_Stream0_IRQn
@ DMA1_Stream0_IRQn
Definition stm32f401xc.h:88
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition stm32f401xc.h:112
SPI4_IRQn
@ SPI4_IRQn
Definition stm32f401xc.h:132
TIM1_UP_TIM10_IRQn
@ TIM1_UP_TIM10_IRQn
Definition stm32f401xc.h:98
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition stm32f401xc.h:96
DMA1_Stream1_IRQn
@ DMA1_Stream1_IRQn
Definition stm32f401xc.h:89
SPI6_IRQn
@ SPI6_IRQn
Definition stm32f427xx.h:162
OTG_FS_IRQn
@ OTG_FS_IRQn
Definition stm32f401xc.h:124
OTG_FS_WKUP_IRQn
@ OTG_FS_WKUP_IRQn
Definition stm32f401xc.h:114
FPU_IRQn
@ FPU_IRQn
Definition stm32f401xc.h:131
TIM8_UP_TIM13_IRQn
@ TIM8_UP_TIM13_IRQn
Definition stm32f405xx.h:121
USART6_IRQn
@ USART6_IRQn
Definition stm32f401xc.h:128
SPI1_IRQn
@ SPI1_IRQn
Definition stm32f401xc.h:108
OTG_HS_IRQn
@ OTG_HS_IRQn
Definition stm32f405xx.h:152
PVD_IRQn
@ PVD_IRQn
Definition stm32f401xc.h:78
TIM1_TRG_COM_TIM11_IRQn
@ TIM1_TRG_COM_TIM11_IRQn
Definition stm32f401xc.h:99
TIM1_BRK_TIM9_IRQn
@ TIM1_BRK_TIM9_IRQn
Definition stm32f401xc.h:97
CAN2_RX1_IRQn
@ CAN2_RX1_IRQn
Definition stm32f405xx.h:140
EXTI0_IRQn
@ EXTI0_IRQn
Definition stm32f401xc.h:83
CAN1_RX0_IRQn
@ CAN1_RX0_IRQn
Definition stm32f405xx.h:97
EXTI4_IRQn
@ EXTI4_IRQn
Definition stm32f401xc.h:87
DMA2_Stream2_IRQn
@ DMA2_Stream2_IRQn
Definition stm32f401xc.h:121
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition stm32f401xc.h:79
UART5_IRQn
@ UART5_IRQn
Definition stm32f405xx.h:130
DMA1_Stream5_IRQn
@ DMA1_Stream5_IRQn
Definition stm32f401xc.h:93
DMA2D_IRQn
@ DMA2D_IRQn
Definition stm32f427xx.h:164
DCMI_IRQn
@ DCMI_IRQn
Definition stm32f407xx.h:155
ETH_IRQn
@ ETH_IRQn
Definition stm32f407xx.h:138
USART1_IRQn
@ USART1_IRQn
Definition stm32f401xc.h:110
EXTI3_IRQn
@ EXTI3_IRQn
Definition stm32f401xc.h:86
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition stm32f401xc.h:68
UART4_IRQn
@ UART4_IRQn
Definition stm32f405xx.h:129
TIM8_TRG_COM_TIM14_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
Definition stm32f405xx.h:122
EXTI1_IRQn
@ EXTI1_IRQn
Definition stm32f401xc.h:84
DMA2_Stream4_IRQn
@ DMA2_Stream4_IRQn
Definition stm32f401xc.h:123
TIM5_IRQn
@ TIM5_IRQn
Definition stm32f401xc.h:117
DMA1_Stream7_IRQn
@ DMA1_Stream7_IRQn
Definition stm32f401xc.h:115
DMA1_Stream4_IRQn
@ DMA1_Stream4_IRQn
Definition stm32f401xc.h:92
DMA1_Stream6_IRQn
@ DMA1_Stream6_IRQn
Definition stm32f401xc.h:94
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition stm32f401xc.h:100
LTDC_IRQn
@ LTDC_IRQn
Definition stm32f429xx.h:164
CAN2_TX_IRQn
@ CAN2_TX_IRQn
Definition stm32f405xx.h:138
CAN1_RX1_IRQn
@ CAN1_RX1_IRQn
Definition stm32f405xx.h:98
DMA1_Stream3_IRQn
@ DMA1_Stream3_IRQn
Definition stm32f401xc.h:91
USART3_IRQn
@ USART3_IRQn
Definition stm32f405xx.h:116
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition stm32f401xc.h:113
ADC_Common_TypeDef
Definition stm32f401xc.h:176
ADC_TypeDef
Analog to Digital Converter.
Definition stm32f401xc.h:152
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition stm32f405xx.h:225
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition stm32f405xx.h:237
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition stm32f405xx.h:213
CAN_TypeDef
Controller Area Network.
Definition stm32f405xx.h:247
CRC_TypeDef
CRC calculation unit.
Definition stm32f401xc.h:188
CRYP_TypeDef
Crypto Processor.
Definition stm32f415xx.h:687
DAC_TypeDef
Digital to Analog Converter.
Definition stm32f405xx.h:290
DBGMCU_TypeDef
Debug MCU.
Definition stm32f401xc.h:201
DCMI_TypeDef
DCMI.
Definition stm32f407xx.h:327
DMA2D_TypeDef
DMA2D Controller.
Definition stm32f427xx.h:373
DMA_Stream_TypeDef
DMA Controller.
Definition stm32f401xc.h:214
DMA_TypeDef
Definition stm32f401xc.h:224
ETH_TypeDef
Ethernet MAC.
Definition stm32f407xx.h:368
EXTI_TypeDef
External Interrupt/Event Controller.
Definition stm32f401xc.h:236
FLASH_TypeDef
FLASH Registers.
Definition stm32f401xc.h:250
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition stm32f427xx.h:508
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition stm32f427xx.h:517
FMC_Bank2_3_TypeDef
Flexible Memory Controller Bank2.
Definition stm32f427xx.h:525
FMC_Bank4_TypeDef
Flexible Memory Controller Bank4.
Definition stm32f427xx.h:547
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5_6.
Definition stm32f427xx.h:560
GPIO_TypeDef
General Purpose I/O.
Definition stm32f401xc.h:265
HASH_DIGEST_TypeDef
HASH_DIGEST.
Definition stm32f415xx.h:747
HASH_TypeDef
HASH.
Definition stm32f415xx.h:731
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition stm32f401xc.h:295
IWDG_TypeDef
Independent WATCHDOG.
Definition stm32f401xc.h:313
LTDC_Layer_TypeDef
LCD-TFT Display layer x Controller.
Definition stm32f429xx.h:660
LTDC_TypeDef
LCD-TFT Display Controller.
Definition stm32f429xx.h:635
PWR_TypeDef
Power Control.
Definition stm32f401xc.h:326
RCC_TypeDef
Reset and Clock Control.
Definition stm32f401xc.h:336
RNG_TypeDef
RNG.
Definition stm32f405xx.h:688
RTC_TypeDef
Real-Time Clock.
Definition stm32f401xc.h:376
SAI_Block_TypeDef
Definition stm32f413xx.h:633
SAI_TypeDef
Serial Audio Interface.
Definition stm32f413xx.h:628
SDIO_TypeDef
SD host Interface.
Definition stm32f401xc.h:424
SPI_TypeDef
Serial Peripheral Interface.
Definition stm32f401xc.h:452
SYSCFG_TypeDef
System configuration controller.
Definition stm32f401xc.h:282
TIM_TypeDef
TIM.
Definition stm32f401xc.h:470
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition stm32f401xc.h:499
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition stm32f401xc.h:548
USB_OTG_GlobalTypeDef
USB_OTG_Core_Registers.
Definition stm32f401xc.h:523
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition stm32f401xc.h:618
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition stm32f401xc.h:604
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition stm32f401xc.h:575
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition stm32f401xc.h:590
WWDG_TypeDef
Window WATCHDOG.
Definition stm32f401xc.h:514
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
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